Fix
This commit is contained in:
parent
cc6c133f41
commit
2327671554
@ -1,13 +1,15 @@
|
||||
#include "app.h"
|
||||
// #include "lwip.h"
|
||||
|
||||
void app() {
|
||||
|
||||
// init_LWIP();
|
||||
init_LWIP();
|
||||
|
||||
while(1) {
|
||||
printf("Test: %d\r\n", 5);
|
||||
// process_LWIP();
|
||||
uint32_t regvalue = 0;
|
||||
HAL_ETH_ReadPHYRegister(getEthStruct(), 1, ®value);
|
||||
delay(500);
|
||||
printf("Test: %d\r\n", regvalue);
|
||||
// process_LWIP();
|
||||
};
|
||||
}
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
#include "app.h"
|
||||
#include "../bsp/bsp.h"
|
||||
|
||||
int main() {
|
||||
board_init();
|
||||
|
||||
@ -1,27 +1,44 @@
|
||||
set(LWIP_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/lwip)
|
||||
set(LWIP_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/lwip/src)
|
||||
set(LWIP_INCLUDES ${CMAKE_CURRENT_SOURCE_DIR}/lwip/src/include)
|
||||
set(LWIP_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/lwip/src/core)
|
||||
|
||||
# file(GLOB_RECURSE LWIP_SOURCES
|
||||
# ${LWIP_SOURCE_DIR}/src/core/*.c
|
||||
# ${LWIP_SOURCE_DIR}/src/netif/*.c
|
||||
# )
|
||||
file(GLOB_RECURSE LWIP_SOURCES
|
||||
${LWIP_SOURCE_DIR}/core/*.c
|
||||
${LWIP_SOURCE_DIR}/netif/*.c
|
||||
)
|
||||
|
||||
add_library(bsp STATIC
|
||||
bsp.c
|
||||
# syscalls.c
|
||||
# lwip/lwip.c
|
||||
# ${LWIP_SOURCES}/init.c
|
||||
# ${LWIP_SOURCES}
|
||||
lwip/lwip.c
|
||||
lwip/ethernetif.c
|
||||
lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c
|
||||
${LWIP_SOURCE_DIR}/api/err.c
|
||||
${LWIP_SOURCE_DIR}/core/def.c
|
||||
${LWIP_SOURCE_DIR}/core/init.c
|
||||
${LWIP_SOURCE_DIR}/core/ip.c
|
||||
${LWIP_SOURCE_DIR}/core/mem.c
|
||||
${LWIP_SOURCE_DIR}/core/memp.c
|
||||
${LWIP_SOURCE_DIR}/core/netif.c
|
||||
${LWIP_SOURCE_DIR}/core/pbuf.c
|
||||
${LWIP_SOURCE_DIR}/core/timeouts.c
|
||||
${LWIP_SOURCE_DIR}/core/udp.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/dhcp.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/etharp.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/icmp.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/ip4.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/ip4_addr.c
|
||||
${LWIP_SOURCE_DIR}/core/ipv4/ip4_frag.c
|
||||
${LWIP_SOURCE_DIR}/netif/ethernet.c
|
||||
)
|
||||
|
||||
target_include_directories(bsp PRIVATE
|
||||
${CMAKE_CURRENT_SOURCE_DIR}
|
||||
# ${CMAKE_SOURCE_DIR}/bsp/lwip
|
||||
# ${CMAKE_SOURCE_DIR}/bsp/lwip/system
|
||||
# ${LWIP_INCLUDES}
|
||||
# ${LWIP_INCLUDES}/lwip
|
||||
# ${LWIP_INCLUDES}/netif
|
||||
${CMAKE_SOURCE_DIR}/bsp/lwip
|
||||
${CMAKE_SOURCE_DIR}/bsp/lwip/system
|
||||
${LWIP_INCLUDES}
|
||||
${LWIP_INCLUDES}/lwip
|
||||
${LWIP_INCLUDES}/netif
|
||||
${LWIP_INCLUDES}/stm32f4_eth_periph/inc
|
||||
)
|
||||
|
||||
target_link_libraries(bsp PUBLIC
|
||||
|
||||
28
bsp/bsp.c
28
bsp/bsp.c
@ -1,7 +1,9 @@
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm32f4xx_dma.h"
|
||||
#include "misc.h"
|
||||
#include "bsp.h"
|
||||
#include "lwip.h"
|
||||
|
||||
#define MAX_DELAY 0xFFFFFFFU
|
||||
#define INTERVAL 500
|
||||
@ -106,27 +108,37 @@ void usart_init() {
|
||||
usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART2, &usart);
|
||||
USART_Cmd(USART2, ENABLE);
|
||||
|
||||
//NVIC_EnableIRQ(USART2_IRQn);
|
||||
}
|
||||
|
||||
void eth_init() {
|
||||
|
||||
void dma_init() {
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
|
||||
DMA_InitTypeDef dma;
|
||||
dma.DMA_Channel = DMA_Channel_0;
|
||||
dma.DMA_DIR = DMA_DIR_MemoryToMemory;
|
||||
dma.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
|
||||
dma.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
dma.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
dma.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
dma.DMA_Mode = DMA_Mode_Normal;
|
||||
dma.DMA_Priority = DMA_Priority_Low;
|
||||
dma.DMA_FIFOMode = DMA_FIFOMode_Enable;
|
||||
dma.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
dma.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
dma.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_Init(DMA2_Stream0, &dma);
|
||||
}
|
||||
|
||||
void board_init() {
|
||||
uint32_t tick = SystemCoreClock/1000;
|
||||
|
||||
SysTick_Config(tick);
|
||||
NVIC_EnableIRQ(SysTick_IRQn);
|
||||
__enable_irq();
|
||||
gpio_init();
|
||||
usart_init();
|
||||
dma_init();
|
||||
init_LWIP();
|
||||
delay(50); //wait until periph init
|
||||
printf("Controller is started...\r\n");
|
||||
}
|
||||
|
||||
// uint32_t getRegister() {
|
||||
// return EthStatus;
|
||||
// }
|
||||
|
||||
|
||||
@ -3,9 +3,9 @@
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "stm32f4xx_usart.h"
|
||||
|
||||
void board_init();
|
||||
uint32_t getRegister();
|
||||
void transmitPacket();
|
||||
uint32_t getSysTick();
|
||||
void delay(uint32_t);
|
||||
|
||||
|
||||
@ -56,13 +56,9 @@
|
||||
#include "netif/etharp.h"
|
||||
#include "lwip/ethip6.h"
|
||||
#include "ethernetif.h"
|
||||
#include "stm32f4xx_hal_eth.h"
|
||||
#include <string.h>
|
||||
|
||||
/* Within 'USER CODE' section, code will be kept by default at each generation */
|
||||
/* USER CODE BEGIN 0 */
|
||||
#include "bsp.h"
|
||||
#include <stdio.h>
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
@ -70,9 +66,6 @@
|
||||
#define IFNAME0 's'
|
||||
#define IFNAME1 't'
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
@ -95,120 +88,13 @@ __ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethe
|
||||
#endif
|
||||
__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
|
||||
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
|
||||
/* Global Ethernet handle */
|
||||
ETH_HandleTypeDef heth;
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
|
||||
/* USER CODE END 3 */
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
// void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
|
||||
// {
|
||||
// GPIO_InitTypeDef GPIO_InitStruct;
|
||||
// if(ethHandle->Instance==ETH)
|
||||
// {
|
||||
// /* USER CODE BEGIN ETH_MspInit 0 */
|
||||
|
||||
// /* USER CODE END ETH_MspInit 0 */
|
||||
// /* Enable Peripheral clock */
|
||||
// __HAL_RCC_ETH_CLK_ENABLE();
|
||||
|
||||
// /**ETH GPIO Configuration
|
||||
// PC1 ------> ETH_MDC
|
||||
// PA1 ------> ETH_REF_CLK
|
||||
// PA2 ------> ETH_MDIO
|
||||
// PA7 ------> ETH_CRS_DV
|
||||
// PC4 ------> ETH_RXD0
|
||||
// PC5 ------> ETH_RXD1
|
||||
// PB13 ------> ETH_TXD1
|
||||
// PG11 ------> ETH_TX_EN
|
||||
// PG13 ------> ETH_TXD0
|
||||
// */
|
||||
// GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
|
||||
// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
// GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
// GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
// HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
// GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
|
||||
// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
// GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
// GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
// HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
// GPIO_InitStruct.Pin = GPIO_PIN_13;
|
||||
// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
// GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
// GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
// GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13;
|
||||
// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
// GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
// GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
// HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
||||
|
||||
// /* Peripheral interrupt init */
|
||||
// HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
|
||||
// HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
// /* USER CODE BEGIN ETH_MspInit 1 */
|
||||
|
||||
// /* USER CODE END ETH_MspInit 1 */
|
||||
// }
|
||||
// }
|
||||
|
||||
// void HAL_ETH_MspDeInit(ETH_HandleTypeDef* ethHandle)
|
||||
// {
|
||||
// if(ethHandle->Instance==ETH)
|
||||
// {
|
||||
// /* USER CODE BEGIN ETH_MspDeInit 0 */
|
||||
|
||||
// /* USER CODE END ETH_MspDeInit 0 */
|
||||
// /* Peripheral clock disable */
|
||||
// __HAL_RCC_ETH_CLK_DISABLE();
|
||||
|
||||
// /**ETH GPIO Configuration
|
||||
// PC1 ------> ETH_MDC
|
||||
// PA1 ------> ETH_REF_CLK
|
||||
// PA2 ------> ETH_MDIO
|
||||
// PA7 ------> ETH_CRS_DV
|
||||
// PC4 ------> ETH_RXD0
|
||||
// PC5 ------> ETH_RXD1
|
||||
// PB13 ------> ETH_TXD1
|
||||
// PG11 ------> ETH_TX_EN
|
||||
// PG13 ------> ETH_TXD0
|
||||
// */
|
||||
// HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
|
||||
|
||||
// HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7);
|
||||
|
||||
// HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
|
||||
// HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13);
|
||||
|
||||
// /* Peripheral interrupt Deinit*/
|
||||
// HAL_NVIC_DisableIRQ(ETH_IRQn);
|
||||
|
||||
// /* USER CODE BEGIN ETH_MspDeInit 1 */
|
||||
|
||||
// /* USER CODE END ETH_MspDeInit 1 */
|
||||
// }
|
||||
// }
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
|
||||
/* USER CODE END 4 */
|
||||
|
||||
ETH_HandleTypeDef* getEthStruct() {
|
||||
return &heth;
|
||||
}
|
||||
/*******************************************************************************
|
||||
LL Driver Interface ( LwIP stack --> ETH)
|
||||
*******************************************************************************/
|
||||
@ -224,7 +110,6 @@ static void low_level_init(struct netif *netif)
|
||||
uint32_t regvalue = 0;
|
||||
HAL_StatusTypeDef hal_eth_init_status;
|
||||
|
||||
/* Init ETH */
|
||||
|
||||
uint8_t MACAddr[6] ;
|
||||
heth.Instance = ETH;
|
||||
@ -241,13 +126,11 @@ static void low_level_init(struct netif *netif)
|
||||
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
|
||||
/* USER CODE BEGIN MACADDRESS */
|
||||
printf("LAN8742A PHYAD: 0x0\r\r\n");
|
||||
printf("Setting MACaddr: %02x:%02x:%02x:%02x:%02x:%02x\r\r\n",
|
||||
MACAddr[0], MACAddr[1], MACAddr[2],
|
||||
MACAddr[3], MACAddr[4], MACAddr[5]);
|
||||
printf("LAN8742A interface is RMII\r\r\n");
|
||||
/* USER CODE END MACADDRESS */
|
||||
|
||||
hal_eth_init_status = HAL_ETH_Init(&heth);
|
||||
|
||||
@ -289,9 +172,9 @@ static void low_level_init(struct netif *netif)
|
||||
/* Enable MAC and DMA transmission and reception */
|
||||
HAL_ETH_Start(&heth);
|
||||
|
||||
/* USER CODE BEGIN PHY_PRE_CONFIG */
|
||||
|
||||
printf("Starting Ethernet IRQ/DMA..\r\r\n");
|
||||
/* USER CODE END PHY_PRE_CONFIG */
|
||||
|
||||
|
||||
|
||||
/* Read Register Configuration */
|
||||
@ -303,33 +186,12 @@ static void low_level_init(struct netif *netif)
|
||||
|
||||
/* Read Register Configuration */
|
||||
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , ®value);
|
||||
printf("Link: %d\r\n", regvalue);
|
||||
|
||||
/* USER CODE BEGIN PHY_POST_CONFIG */
|
||||
#endif
|
||||
|
||||
/* USER CODE END PHY_POST_CONFIG */
|
||||
|
||||
#endif /* LWIP_ARP || LWIP_ETHERNET */
|
||||
|
||||
/* USER CODE BEGIN LOW_LEVEL_INIT */
|
||||
|
||||
/* USER CODE END LOW_LEVEL_INIT */
|
||||
}
|
||||
|
||||
/**
|
||||
* This function should do the actual transmission of the packet. The packet is
|
||||
* contained in the pbuf that is passed to the function. This pbuf
|
||||
* might be chained.
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
|
||||
* @return ERR_OK if the packet could be sent
|
||||
* an err_t value if the packet couldn't be sent
|
||||
*
|
||||
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
|
||||
* strange results. You might consider waiting for space in the DMA queue
|
||||
* to become availale since the stack doesn't retry to send a packet
|
||||
* dropped because of memory failure (except for the TCP timers).
|
||||
*/
|
||||
|
||||
static err_t low_level_output(struct netif *netif, struct pbuf *p)
|
||||
{
|
||||
@ -538,10 +400,6 @@ static err_t low_level_output_arp_off(struct netif *netif, struct pbuf *q, const
|
||||
err_t errval;
|
||||
errval = ERR_OK;
|
||||
|
||||
/* USER CODE BEGIN 5 */
|
||||
|
||||
/* USER CODE END 5 */
|
||||
|
||||
return errval;
|
||||
|
||||
}
|
||||
@ -598,8 +456,6 @@ err_t ethernetif_init(struct netif *netif)
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 6 */
|
||||
|
||||
/**
|
||||
* @brief Returns the current time in milliseconds
|
||||
* when LWIP_TIMERS == 1 and NO_SYS == 1
|
||||
@ -622,12 +478,6 @@ u32_t sys_now(void)
|
||||
return getSysTick();
|
||||
}
|
||||
|
||||
/* USER CODE END 6 */
|
||||
|
||||
/* USER CODE BEGIN 7 */
|
||||
|
||||
/* USER CODE END 7 */
|
||||
|
||||
#if LWIP_NETIF_LINK_CALLBACK
|
||||
/**
|
||||
* @brief Link callback function, this function is called on change of link status
|
||||
@ -717,7 +567,6 @@ void ethernetif_update_config(struct netif *netif)
|
||||
ethernetif_notify_conn_changed(netif);
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 8 */
|
||||
/**
|
||||
* @brief This function notify user about link status changement.
|
||||
* @param netif: the network interface
|
||||
@ -730,11 +579,7 @@ __weak void ethernetif_notify_conn_changed(struct netif *netif)
|
||||
*/
|
||||
|
||||
}
|
||||
/* USER CODE END 8 */
|
||||
#endif /* LWIP_NETIF_LINK_CALLBACK */
|
||||
|
||||
/* USER CODE BEGIN 9 */
|
||||
|
||||
/* USER CODE END 9 */
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/netif.h"
|
||||
#include "stm32f4xx_hal_eth.h"
|
||||
|
||||
err_t ethernetif_init(struct netif *netif);
|
||||
|
||||
@ -12,7 +13,6 @@ void ethernetif_notify_conn_changed(struct netif *netif);
|
||||
|
||||
u32_t sys_jiffies(void);
|
||||
u32_t sys_now(void);
|
||||
|
||||
ETH_HandleTypeDef* getEthStruct();
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@ -1,64 +1,72 @@
|
||||
#include "lwip.h"
|
||||
#include "lwip/init.h"
|
||||
// #include "lwip/netif.h"
|
||||
// #include "lwip/opt.h"
|
||||
// #include "lwip/mem.h"
|
||||
// #include "lwip/memp.h"
|
||||
// #include "netif/etharp.h"
|
||||
// #include "lwip/timeouts.h"
|
||||
// #include "ethernetif.h"
|
||||
#include "lwip/netif.h"
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/mem.h"
|
||||
#include "lwip/memp.h"
|
||||
#include "lwip/udp.h"
|
||||
#include "netif/etharp.h"
|
||||
#include "lwip/timeouts.h"
|
||||
#include "ethernetif.h"
|
||||
|
||||
void Error_Handler(void);
|
||||
|
||||
// /* DHCP Variables initialization ---------------------------------------------*/
|
||||
// uint32_t DHCPfineTimer = 0;
|
||||
// uint32_t DHCPcoarseTimer = 0;
|
||||
|
||||
// struct netif gnetif;
|
||||
// ip4_addr_t ipaddr;
|
||||
// ip4_addr_t netmask;
|
||||
// ip4_addr_t gw;
|
||||
struct netif gnetif;
|
||||
ip4_addr_t ipaddr;
|
||||
ip4_addr_t netmask;
|
||||
ip4_addr_t gw;
|
||||
uint8_t IP_ADDRESS[4];
|
||||
uint8_t NETMASK_ADDRESS[4];
|
||||
uint8_t GATEWAY_ADDRESS[4];
|
||||
|
||||
err_t udp_client_init();
|
||||
|
||||
void init_LWIP(void)
|
||||
{
|
||||
IP_ADDRESS[0] = 192;
|
||||
IP_ADDRESS[1] = 168;
|
||||
IP_ADDRESS[2] = 0;
|
||||
IP_ADDRESS[3] = 66;
|
||||
NETMASK_ADDRESS[0] = 255;
|
||||
NETMASK_ADDRESS[1] = 255;
|
||||
NETMASK_ADDRESS[2] = 0;
|
||||
NETMASK_ADDRESS[3] = 0;
|
||||
GATEWAY_ADDRESS[0] = 0;
|
||||
GATEWAY_ADDRESS[1] = 0;
|
||||
GATEWAY_ADDRESS[2] = 0;
|
||||
GATEWAY_ADDRESS[3] = 0;
|
||||
|
||||
/* Initilialize the LwIP stack without RTOS */
|
||||
lwip_init();
|
||||
|
||||
// /* IP addresses initialization with DHCP (IPv4) */
|
||||
// ipaddr.addr = 0;
|
||||
// netmask.addr = 0;
|
||||
// gw.addr = 0;
|
||||
IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]);
|
||||
IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]);
|
||||
IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]);
|
||||
|
||||
// /* add the network interface (IPv4b/IPv6) without RTOS */
|
||||
// netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input);
|
||||
/* add the network interface (IPv4b/IPv6) without RTOS */
|
||||
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input);
|
||||
|
||||
// /* Registers the default network interface */
|
||||
// netif_set_default(&gnetif);
|
||||
|
||||
// if (netif_is_link_up(&gnetif))
|
||||
// {
|
||||
// /* When the netif is fully configured this function must be called */
|
||||
// netif_set_up(&gnetif);
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// /* When the netif link is down this function must be called */
|
||||
// netif_set_down(&gnetif);
|
||||
// }
|
||||
|
||||
/* Start DHCP negotiation for a network interface (IPv4) */
|
||||
//dhcp_start(&gnetif);
|
||||
netif_set_default(&gnetif);
|
||||
|
||||
if (netif_is_link_up(&gnetif))
|
||||
{
|
||||
/* When the netif is fully configured this function must be called */
|
||||
netif_set_up(&gnetif);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* When the netif link is down this function must be called */
|
||||
netif_set_down(&gnetif);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void process_LWIP(void)
|
||||
void process_LWIP()
|
||||
{
|
||||
|
||||
// ethernetif_input(&gnetif);
|
||||
|
||||
// sys_check_timeouts();
|
||||
ethernetif_input(&gnetif);
|
||||
sys_check_timeouts();
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -144,6 +144,10 @@
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 1 */
|
||||
#define LWIP_DEBUG 1
|
||||
|
||||
#define LWIP_UDP 1
|
||||
|
||||
#define LWIP_TCP 0
|
||||
/* USER CODE END 1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
2241
bsp/lwip/stm32f4_eth_periph/inc/stm32f4xx_hal_eth.h
Normal file
2241
bsp/lwip/stm32f4_eth_periph/inc/stm32f4xx_hal_eth.h
Normal file
File diff suppressed because it is too large
Load Diff
2062
bsp/lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c
Normal file
2062
bsp/lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -5,7 +5,6 @@ get_filename_component(LINKER_SCRIPT src/stm32f439zi_flash.ld ABSOLUTE)
|
||||
|
||||
add_library(stm32f4xx STATIC
|
||||
src/STM32F4xx_StdPeriph_Driver/misc.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth_bsp.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_adc.c
|
||||
@ -18,7 +17,7 @@ add_library(stm32f4xx STATIC
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dac.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dbgmcu.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dcmi.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dma.c
|
||||
src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dma.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_exti.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_flash.c
|
||||
# src/STM32F4xx_StdPeriph_Driver/stm32f4xx_fsmc.c
|
||||
|
||||
@ -204,6 +204,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
|
||||
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
RCC_APB2ENR_SYSCFGEN
|
||||
|
||||
/* Select MII or RMII Mode*/
|
||||
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
|
||||
@ -241,7 +242,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
|
||||
tmpreg1 &= ETH_MACMIIAR_CR_MASK;
|
||||
|
||||
/* Get hclk frequency value */
|
||||
hclk = HAL_RCC_GetHCLKFreq();
|
||||
hclk = SystemCoreClock;
|
||||
|
||||
/* Set CR bits depending on hclk value */
|
||||
if((hclk >= 20000000U)&&(hclk < 35000000U))
|
||||
|
||||
791
objdump_elf
791
objdump_elf
@ -1,791 +0,0 @@
|
||||
|
||||
build/bin/stm32.elf: file format elf32-littlearm
|
||||
|
||||
|
||||
Disassembly of section .isr_vector:
|
||||
|
||||
08000000 <g_pfnVectors>:
|
||||
8000000: 20030000 andcs r0, r3, r0
|
||||
8000004: 080004d1 stmdaeq r0, {r0, r4, r6, r7, sl}
|
||||
8000008: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800000c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000010: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000014: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000018: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
...
|
||||
800002c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000030: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000034: 00000000 andeq r0, r0, r0
|
||||
8000038: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800003c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000040: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000044: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000048: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800004c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000050: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000054: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000058: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800005c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000060: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000064: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000068: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800006c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000070: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000074: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000078: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800007c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000080: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000084: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000088: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800008c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000090: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000094: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000098: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800009c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000a0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000a4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000a8: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000ac: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000b0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000b4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000b8: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000bc: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000c0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000c4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000c8: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000cc: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000d0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000d4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000d8: 08000197 stmdaeq r0, {r0, r1, r2, r4, r7, r8}
|
||||
80000dc: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000e0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000e4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000e8: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000ec: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000f0: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000f4: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000f8: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
80000fc: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000100: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000104: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000108: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800010c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000110: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000114: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000118: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800011c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000120: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000124: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000128: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800012c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000130: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000134: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000138: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800013c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000140: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000144: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000148: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800014c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000150: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000154: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000158: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800015c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000160: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000164: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000168: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800016c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000170: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000174: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000178: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
800017c: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000180: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
8000184: 08000515 stmdaeq r0, {r0, r2, r4, r8, sl}
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
08000188 <main>:
|
||||
8000188: b580 push {r7, lr}
|
||||
800018a: af00 add r7, sp, #0
|
||||
800018c: f000 f81f bl 80001ce <board_init>
|
||||
8000190: 2300 movs r3, #0
|
||||
8000192: 4618 mov r0, r3
|
||||
8000194: bd80 pop {r7, pc}
|
||||
|
||||
08000196 <USART2_IRQHandler>:
|
||||
8000196: b480 push {r7}
|
||||
8000198: af00 add r7, sp, #0
|
||||
800019a: bf00 nop
|
||||
800019c: 46bd mov sp, r7
|
||||
800019e: f85d 7b04 ldr.w r7, [sp], #4
|
||||
80001a2: 4770 bx lr
|
||||
|
||||
080001a4 <gpio_init>:
|
||||
80001a4: b480 push {r7}
|
||||
80001a6: af00 add r7, sp, #0
|
||||
80001a8: bf00 nop
|
||||
80001aa: 46bd mov sp, r7
|
||||
80001ac: f85d 7b04 ldr.w r7, [sp], #4
|
||||
80001b0: 4770 bx lr
|
||||
|
||||
080001b2 <usart_init>:
|
||||
80001b2: b480 push {r7}
|
||||
80001b4: af00 add r7, sp, #0
|
||||
80001b6: bf00 nop
|
||||
80001b8: 46bd mov sp, r7
|
||||
80001ba: f85d 7b04 ldr.w r7, [sp], #4
|
||||
80001be: 4770 bx lr
|
||||
|
||||
080001c0 <eth_init>:
|
||||
80001c0: b480 push {r7}
|
||||
80001c2: af00 add r7, sp, #0
|
||||
80001c4: bf00 nop
|
||||
80001c6: 46bd mov sp, r7
|
||||
80001c8: f85d 7b04 ldr.w r7, [sp], #4
|
||||
80001cc: 4770 bx lr
|
||||
|
||||
080001ce <board_init>:
|
||||
80001ce: b480 push {r7}
|
||||
80001d0: af00 add r7, sp, #0
|
||||
80001d2: bf00 nop
|
||||
80001d4: 46bd mov sp, r7
|
||||
80001d6: f85d 7b04 ldr.w r7, [sp], #4
|
||||
80001da: 4770 bx lr
|
||||
|
||||
080001dc <SystemInit>:
|
||||
80001dc: b580 push {r7, lr}
|
||||
80001de: af00 add r7, sp, #0
|
||||
80001e0: 4b16 ldr r3, [pc, #88] @ (800023c <SystemInit+0x60>)
|
||||
80001e2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
||||
80001e6: 4a15 ldr r2, [pc, #84] @ (800023c <SystemInit+0x60>)
|
||||
80001e8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
||||
80001ec: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
||||
80001f0: 4b13 ldr r3, [pc, #76] @ (8000240 <SystemInit+0x64>)
|
||||
80001f2: 681b ldr r3, [r3, #0]
|
||||
80001f4: 4a12 ldr r2, [pc, #72] @ (8000240 <SystemInit+0x64>)
|
||||
80001f6: f043 0301 orr.w r3, r3, #1
|
||||
80001fa: 6013 str r3, [r2, #0]
|
||||
80001fc: 4b10 ldr r3, [pc, #64] @ (8000240 <SystemInit+0x64>)
|
||||
80001fe: 2200 movs r2, #0
|
||||
8000200: 609a str r2, [r3, #8]
|
||||
8000202: 4b0f ldr r3, [pc, #60] @ (8000240 <SystemInit+0x64>)
|
||||
8000204: 681b ldr r3, [r3, #0]
|
||||
8000206: 4a0e ldr r2, [pc, #56] @ (8000240 <SystemInit+0x64>)
|
||||
8000208: f023 7384 bic.w r3, r3, #17301504 @ 0x1080000
|
||||
800020c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
||||
8000210: 6013 str r3, [r2, #0]
|
||||
8000212: 4b0b ldr r3, [pc, #44] @ (8000240 <SystemInit+0x64>)
|
||||
8000214: 4a0b ldr r2, [pc, #44] @ (8000244 <SystemInit+0x68>)
|
||||
8000216: 605a str r2, [r3, #4]
|
||||
8000218: 4b09 ldr r3, [pc, #36] @ (8000240 <SystemInit+0x64>)
|
||||
800021a: 681b ldr r3, [r3, #0]
|
||||
800021c: 4a08 ldr r2, [pc, #32] @ (8000240 <SystemInit+0x64>)
|
||||
800021e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
||||
8000222: 6013 str r3, [r2, #0]
|
||||
8000224: 4b06 ldr r3, [pc, #24] @ (8000240 <SystemInit+0x64>)
|
||||
8000226: 2200 movs r2, #0
|
||||
8000228: 60da str r2, [r3, #12]
|
||||
800022a: f000 f88f bl 800034c <SetSysClock>
|
||||
800022e: 4b03 ldr r3, [pc, #12] @ (800023c <SystemInit+0x60>)
|
||||
8000230: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
||||
8000234: 609a str r2, [r3, #8]
|
||||
8000236: bf00 nop
|
||||
8000238: bd80 pop {r7, pc}
|
||||
800023a: bf00 nop
|
||||
800023c: e000ed00 and lr, r0, r0, lsl #26
|
||||
8000240: 40023800 andmi r3, r2, r0, lsl #16
|
||||
8000244: 24003010 strcs r3, [r0], #-16
|
||||
|
||||
08000248 <SystemCoreClockUpdate>:
|
||||
8000248: b480 push {r7}
|
||||
800024a: b087 sub sp, #28
|
||||
800024c: af00 add r7, sp, #0
|
||||
800024e: 2300 movs r3, #0
|
||||
8000250: 613b str r3, [r7, #16]
|
||||
8000252: 2300 movs r3, #0
|
||||
8000254: 617b str r3, [r7, #20]
|
||||
8000256: 2302 movs r3, #2
|
||||
8000258: 60fb str r3, [r7, #12]
|
||||
800025a: 2300 movs r3, #0
|
||||
800025c: 60bb str r3, [r7, #8]
|
||||
800025e: 2302 movs r3, #2
|
||||
8000260: 607b str r3, [r7, #4]
|
||||
8000262: 4b35 ldr r3, [pc, #212] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
8000264: 689b ldr r3, [r3, #8]
|
||||
8000266: f003 030c and.w r3, r3, #12
|
||||
800026a: 613b str r3, [r7, #16]
|
||||
800026c: 693b ldr r3, [r7, #16]
|
||||
800026e: 2b08 cmp r3, #8
|
||||
8000270: d011 beq.n 8000296 <SystemCoreClockUpdate+0x4e>
|
||||
8000272: 693b ldr r3, [r7, #16]
|
||||
8000274: 2b08 cmp r3, #8
|
||||
8000276: d844 bhi.n 8000302 <SystemCoreClockUpdate+0xba>
|
||||
8000278: 693b ldr r3, [r7, #16]
|
||||
800027a: 2b00 cmp r3, #0
|
||||
800027c: d003 beq.n 8000286 <SystemCoreClockUpdate+0x3e>
|
||||
800027e: 693b ldr r3, [r7, #16]
|
||||
8000280: 2b04 cmp r3, #4
|
||||
8000282: d004 beq.n 800028e <SystemCoreClockUpdate+0x46>
|
||||
8000284: e03d b.n 8000302 <SystemCoreClockUpdate+0xba>
|
||||
8000286: 4b2d ldr r3, [pc, #180] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
8000288: 4a2d ldr r2, [pc, #180] @ (8000340 <SystemCoreClockUpdate+0xf8>)
|
||||
800028a: 601a str r2, [r3, #0]
|
||||
800028c: e03d b.n 800030a <SystemCoreClockUpdate+0xc2>
|
||||
800028e: 4b2b ldr r3, [pc, #172] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
8000290: 4a2c ldr r2, [pc, #176] @ (8000344 <SystemCoreClockUpdate+0xfc>)
|
||||
8000292: 601a str r2, [r3, #0]
|
||||
8000294: e039 b.n 800030a <SystemCoreClockUpdate+0xc2>
|
||||
8000296: 4b28 ldr r3, [pc, #160] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
8000298: 685b ldr r3, [r3, #4]
|
||||
800029a: 0d9b lsrs r3, r3, #22
|
||||
800029c: f003 0301 and.w r3, r3, #1
|
||||
80002a0: 60bb str r3, [r7, #8]
|
||||
80002a2: 4b25 ldr r3, [pc, #148] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
80002a4: 685b ldr r3, [r3, #4]
|
||||
80002a6: f003 033f and.w r3, r3, #63 @ 0x3f
|
||||
80002aa: 607b str r3, [r7, #4]
|
||||
80002ac: 68bb ldr r3, [r7, #8]
|
||||
80002ae: 2b00 cmp r3, #0
|
||||
80002b0: d00c beq.n 80002cc <SystemCoreClockUpdate+0x84>
|
||||
80002b2: 4a24 ldr r2, [pc, #144] @ (8000344 <SystemCoreClockUpdate+0xfc>)
|
||||
80002b4: 687b ldr r3, [r7, #4]
|
||||
80002b6: fbb2 f3f3 udiv r3, r2, r3
|
||||
80002ba: 4a1f ldr r2, [pc, #124] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
80002bc: 6852 ldr r2, [r2, #4]
|
||||
80002be: 0992 lsrs r2, r2, #6
|
||||
80002c0: f3c2 0208 ubfx r2, r2, #0, #9
|
||||
80002c4: fb02 f303 mul.w r3, r2, r3
|
||||
80002c8: 617b str r3, [r7, #20]
|
||||
80002ca: e00b b.n 80002e4 <SystemCoreClockUpdate+0x9c>
|
||||
80002cc: 4a1c ldr r2, [pc, #112] @ (8000340 <SystemCoreClockUpdate+0xf8>)
|
||||
80002ce: 687b ldr r3, [r7, #4]
|
||||
80002d0: fbb2 f3f3 udiv r3, r2, r3
|
||||
80002d4: 4a18 ldr r2, [pc, #96] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
80002d6: 6852 ldr r2, [r2, #4]
|
||||
80002d8: 0992 lsrs r2, r2, #6
|
||||
80002da: f3c2 0208 ubfx r2, r2, #0, #9
|
||||
80002de: fb02 f303 mul.w r3, r2, r3
|
||||
80002e2: 617b str r3, [r7, #20]
|
||||
80002e4: 4b14 ldr r3, [pc, #80] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
80002e6: 685b ldr r3, [r3, #4]
|
||||
80002e8: 0c1b lsrs r3, r3, #16
|
||||
80002ea: f003 0303 and.w r3, r3, #3
|
||||
80002ee: 3301 adds r3, #1
|
||||
80002f0: 005b lsls r3, r3, #1
|
||||
80002f2: 60fb str r3, [r7, #12]
|
||||
80002f4: 697a ldr r2, [r7, #20]
|
||||
80002f6: 68fb ldr r3, [r7, #12]
|
||||
80002f8: fbb2 f3f3 udiv r3, r2, r3
|
||||
80002fc: 4a0f ldr r2, [pc, #60] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
80002fe: 6013 str r3, [r2, #0]
|
||||
8000300: e003 b.n 800030a <SystemCoreClockUpdate+0xc2>
|
||||
8000302: 4b0e ldr r3, [pc, #56] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
8000304: 4a0e ldr r2, [pc, #56] @ (8000340 <SystemCoreClockUpdate+0xf8>)
|
||||
8000306: 601a str r2, [r3, #0]
|
||||
8000308: bf00 nop
|
||||
800030a: 4b0b ldr r3, [pc, #44] @ (8000338 <SystemCoreClockUpdate+0xf0>)
|
||||
800030c: 689b ldr r3, [r3, #8]
|
||||
800030e: 091b lsrs r3, r3, #4
|
||||
8000310: f003 030f and.w r3, r3, #15
|
||||
8000314: 4a0c ldr r2, [pc, #48] @ (8000348 <SystemCoreClockUpdate+0x100>)
|
||||
8000316: 5cd3 ldrb r3, [r2, r3]
|
||||
8000318: b2db uxtb r3, r3
|
||||
800031a: 613b str r3, [r7, #16]
|
||||
800031c: 4b07 ldr r3, [pc, #28] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
800031e: 681a ldr r2, [r3, #0]
|
||||
8000320: 693b ldr r3, [r7, #16]
|
||||
8000322: fa22 f303 lsr.w r3, r2, r3
|
||||
8000326: 4a05 ldr r2, [pc, #20] @ (800033c <SystemCoreClockUpdate+0xf4>)
|
||||
8000328: 6013 str r3, [r2, #0]
|
||||
800032a: bf00 nop
|
||||
800032c: 371c adds r7, #28
|
||||
800032e: 46bd mov sp, r7
|
||||
8000330: f85d 7b04 ldr.w r7, [sp], #4
|
||||
8000334: 4770 bx lr
|
||||
8000336: bf00 nop
|
||||
8000338: 40023800 andmi r3, r2, r0, lsl #16
|
||||
800033c: 20000000 andcs r0, r0, r0
|
||||
8000340: 00f42400 rscseq r2, r4, r0, lsl #8
|
||||
8000344: 007a1200 rsbseq r1, sl, r0, lsl #4
|
||||
8000348: 08000600 stmdaeq r0, {r9, sl}
|
||||
|
||||
0800034c <SetSysClock>:
|
||||
800034c: b480 push {r7}
|
||||
800034e: b083 sub sp, #12
|
||||
8000350: af00 add r7, sp, #0
|
||||
8000352: 2300 movs r3, #0
|
||||
8000354: 607b str r3, [r7, #4]
|
||||
8000356: 2300 movs r3, #0
|
||||
8000358: 603b str r3, [r7, #0]
|
||||
800035a: 4b36 ldr r3, [pc, #216] @ (8000434 <SetSysClock+0xe8>)
|
||||
800035c: 681b ldr r3, [r3, #0]
|
||||
800035e: 4a35 ldr r2, [pc, #212] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000360: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
||||
8000364: 6013 str r3, [r2, #0]
|
||||
8000366: 4b33 ldr r3, [pc, #204] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000368: 681b ldr r3, [r3, #0]
|
||||
800036a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
||||
800036e: 603b str r3, [r7, #0]
|
||||
8000370: 687b ldr r3, [r7, #4]
|
||||
8000372: 3301 adds r3, #1
|
||||
8000374: 607b str r3, [r7, #4]
|
||||
8000376: 683b ldr r3, [r7, #0]
|
||||
8000378: 2b00 cmp r3, #0
|
||||
800037a: d103 bne.n 8000384 <SetSysClock+0x38>
|
||||
800037c: 687b ldr r3, [r7, #4]
|
||||
800037e: f5b3 6fa0 cmp.w r3, #1280 @ 0x500
|
||||
8000382: d1f0 bne.n 8000366 <SetSysClock+0x1a>
|
||||
8000384: 4b2b ldr r3, [pc, #172] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000386: 681b ldr r3, [r3, #0]
|
||||
8000388: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
||||
800038c: 2b00 cmp r3, #0
|
||||
800038e: d002 beq.n 8000396 <SetSysClock+0x4a>
|
||||
8000390: 2301 movs r3, #1
|
||||
8000392: 603b str r3, [r7, #0]
|
||||
8000394: e001 b.n 800039a <SetSysClock+0x4e>
|
||||
8000396: 2300 movs r3, #0
|
||||
8000398: 603b str r3, [r7, #0]
|
||||
800039a: 683b ldr r3, [r7, #0]
|
||||
800039c: 2b01 cmp r3, #1
|
||||
800039e: d142 bne.n 8000426 <SetSysClock+0xda>
|
||||
80003a0: 4b24 ldr r3, [pc, #144] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003a2: 6c1b ldr r3, [r3, #64] @ 0x40
|
||||
80003a4: 4a23 ldr r2, [pc, #140] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003a6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
||||
80003aa: 6413 str r3, [r2, #64] @ 0x40
|
||||
80003ac: 4b22 ldr r3, [pc, #136] @ (8000438 <SetSysClock+0xec>)
|
||||
80003ae: 681b ldr r3, [r3, #0]
|
||||
80003b0: 4a21 ldr r2, [pc, #132] @ (8000438 <SetSysClock+0xec>)
|
||||
80003b2: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
||||
80003b6: 6013 str r3, [r2, #0]
|
||||
80003b8: 4b1e ldr r3, [pc, #120] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003ba: 4a1e ldr r2, [pc, #120] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003bc: 689b ldr r3, [r3, #8]
|
||||
80003be: 6093 str r3, [r2, #8]
|
||||
80003c0: 4b1c ldr r3, [pc, #112] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003c2: 689b ldr r3, [r3, #8]
|
||||
80003c4: 4a1b ldr r2, [pc, #108] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003c6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
||||
80003ca: 6093 str r3, [r2, #8]
|
||||
80003cc: 4b19 ldr r3, [pc, #100] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003ce: 689b ldr r3, [r3, #8]
|
||||
80003d0: 4a18 ldr r2, [pc, #96] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003d2: f443 53a0 orr.w r3, r3, #5120 @ 0x1400
|
||||
80003d6: 6093 str r3, [r2, #8]
|
||||
80003d8: 4b16 ldr r3, [pc, #88] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003da: 4a18 ldr r2, [pc, #96] @ (800043c <SetSysClock+0xf0>)
|
||||
80003dc: 605a str r2, [r3, #4]
|
||||
80003de: 4b15 ldr r3, [pc, #84] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003e0: 681b ldr r3, [r3, #0]
|
||||
80003e2: 4a14 ldr r2, [pc, #80] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003e4: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
||||
80003e8: 6013 str r3, [r2, #0]
|
||||
80003ea: bf00 nop
|
||||
80003ec: 4b11 ldr r3, [pc, #68] @ (8000434 <SetSysClock+0xe8>)
|
||||
80003ee: 681b ldr r3, [r3, #0]
|
||||
80003f0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
||||
80003f4: 2b00 cmp r3, #0
|
||||
80003f6: d0f9 beq.n 80003ec <SetSysClock+0xa0>
|
||||
80003f8: 4b11 ldr r3, [pc, #68] @ (8000440 <SetSysClock+0xf4>)
|
||||
80003fa: f240 6205 movw r2, #1541 @ 0x605
|
||||
80003fe: 601a str r2, [r3, #0]
|
||||
8000400: 4b0c ldr r3, [pc, #48] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000402: 689b ldr r3, [r3, #8]
|
||||
8000404: 4a0b ldr r2, [pc, #44] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000406: f023 0303 bic.w r3, r3, #3
|
||||
800040a: 6093 str r3, [r2, #8]
|
||||
800040c: 4b09 ldr r3, [pc, #36] @ (8000434 <SetSysClock+0xe8>)
|
||||
800040e: 689b ldr r3, [r3, #8]
|
||||
8000410: 4a08 ldr r2, [pc, #32] @ (8000434 <SetSysClock+0xe8>)
|
||||
8000412: f043 0302 orr.w r3, r3, #2
|
||||
8000416: 6093 str r3, [r2, #8]
|
||||
8000418: bf00 nop
|
||||
800041a: 4b06 ldr r3, [pc, #24] @ (8000434 <SetSysClock+0xe8>)
|
||||
800041c: 689b ldr r3, [r3, #8]
|
||||
800041e: f003 030c and.w r3, r3, #12
|
||||
8000422: 2b08 cmp r3, #8
|
||||
8000424: d1f9 bne.n 800041a <SetSysClock+0xce>
|
||||
8000426: bf00 nop
|
||||
8000428: 370c adds r7, #12
|
||||
800042a: 46bd mov sp, r7
|
||||
800042c: f85d 7b04 ldr.w r7, [sp], #4
|
||||
8000430: 4770 bx lr
|
||||
8000432: bf00 nop
|
||||
8000434: 40023800 andmi r3, r2, r0, lsl #16
|
||||
8000438: 40007000 andmi r7, r0, r0
|
||||
800043c: 07405408 strbeq r5, [r0, -r8, lsl #8]
|
||||
8000440: 40023c00 andmi r3, r2, r0, lsl #24
|
||||
|
||||
08000444 <deregister_tm_clones>:
|
||||
8000444: 4803 ldr r0, [pc, #12] @ (8000454 <deregister_tm_clones+0x10>)
|
||||
8000446: 4b04 ldr r3, [pc, #16] @ (8000458 <deregister_tm_clones+0x14>)
|
||||
8000448: 4283 cmp r3, r0
|
||||
800044a: d002 beq.n 8000452 <deregister_tm_clones+0xe>
|
||||
800044c: 4b03 ldr r3, [pc, #12] @ (800045c <deregister_tm_clones+0x18>)
|
||||
800044e: b103 cbz r3, 8000452 <deregister_tm_clones+0xe>
|
||||
8000450: 4718 bx r3
|
||||
8000452: 4770 bx lr
|
||||
8000454: 20000008 andcs r0, r0, r8
|
||||
8000458: 20000008 andcs r0, r0, r8
|
||||
800045c: 00000000 andeq r0, r0, r0
|
||||
|
||||
08000460 <register_tm_clones>:
|
||||
8000460: 4805 ldr r0, [pc, #20] @ (8000478 <register_tm_clones+0x18>)
|
||||
8000462: 4b06 ldr r3, [pc, #24] @ (800047c <register_tm_clones+0x1c>)
|
||||
8000464: 1a1b subs r3, r3, r0
|
||||
8000466: 0fd9 lsrs r1, r3, #31
|
||||
8000468: eb01 01a3 add.w r1, r1, r3, asr #2
|
||||
800046c: 1049 asrs r1, r1, #1
|
||||
800046e: d002 beq.n 8000476 <register_tm_clones+0x16>
|
||||
8000470: 4b03 ldr r3, [pc, #12] @ (8000480 <register_tm_clones+0x20>)
|
||||
8000472: b103 cbz r3, 8000476 <register_tm_clones+0x16>
|
||||
8000474: 4718 bx r3
|
||||
8000476: 4770 bx lr
|
||||
8000478: 20000008 andcs r0, r0, r8
|
||||
800047c: 20000008 andcs r0, r0, r8
|
||||
8000480: 00000000 andeq r0, r0, r0
|
||||
|
||||
08000484 <__do_global_dtors_aux>:
|
||||
8000484: b510 push {r4, lr}
|
||||
8000486: 4c06 ldr r4, [pc, #24] @ (80004a0 <__do_global_dtors_aux+0x1c>)
|
||||
8000488: 7823 ldrb r3, [r4, #0]
|
||||
800048a: b943 cbnz r3, 800049e <__do_global_dtors_aux+0x1a>
|
||||
800048c: f7ff ffda bl 8000444 <deregister_tm_clones>
|
||||
8000490: 4b04 ldr r3, [pc, #16] @ (80004a4 <__do_global_dtors_aux+0x20>)
|
||||
8000492: b113 cbz r3, 800049a <__do_global_dtors_aux+0x16>
|
||||
8000494: 4804 ldr r0, [pc, #16] @ (80004a8 <__do_global_dtors_aux+0x24>)
|
||||
8000496: f3af 8000 nop.w
|
||||
800049a: 2301 movs r3, #1
|
||||
800049c: 7023 strb r3, [r4, #0]
|
||||
800049e: bd10 pop {r4, pc}
|
||||
80004a0: 20000008 andcs r0, r0, r8
|
||||
80004a4: 00000000 andeq r0, r0, r0
|
||||
80004a8: 080005e8 stmdaeq r0, {r3, r5, r6, r7, r8, sl}
|
||||
|
||||
080004ac <frame_dummy>:
|
||||
80004ac: b508 push {r3, lr}
|
||||
80004ae: 4b05 ldr r3, [pc, #20] @ (80004c4 <frame_dummy+0x18>)
|
||||
80004b0: b11b cbz r3, 80004ba <frame_dummy+0xe>
|
||||
80004b2: 4905 ldr r1, [pc, #20] @ (80004c8 <frame_dummy+0x1c>)
|
||||
80004b4: 4805 ldr r0, [pc, #20] @ (80004cc <frame_dummy+0x20>)
|
||||
80004b6: f3af 8000 nop.w
|
||||
80004ba: e8bd 4008 ldmia.w sp!, {r3, lr}
|
||||
80004be: f7ff bfcf b.w 8000460 <register_tm_clones>
|
||||
80004c2: bf00 nop
|
||||
80004c4: 00000000 andeq r0, r0, r0
|
||||
80004c8: 2000000c andcs r0, r0, ip
|
||||
80004cc: 080005e8 stmdaeq r0, {r3, r5, r6, r7, r8, sl}
|
||||
|
||||
080004d0 <Reset_Handler>:
|
||||
80004d0: 2100 movs r1, #0
|
||||
80004d2: e003 b.n 80004dc <LoopCopyDataInit>
|
||||
|
||||
080004d4 <CopyDataInit>:
|
||||
80004d4: 4b0a ldr r3, [pc, #40] @ (8000500 <LoopFillZerobss+0x10>)
|
||||
80004d6: 585b ldr r3, [r3, r1]
|
||||
80004d8: 5043 str r3, [r0, r1]
|
||||
80004da: 3104 adds r1, #4
|
||||
|
||||
080004dc <LoopCopyDataInit>:
|
||||
80004dc: 4809 ldr r0, [pc, #36] @ (8000504 <LoopFillZerobss+0x14>)
|
||||
80004de: 4b0a ldr r3, [pc, #40] @ (8000508 <LoopFillZerobss+0x18>)
|
||||
80004e0: 1842 adds r2, r0, r1
|
||||
80004e2: 429a cmp r2, r3
|
||||
80004e4: d3f6 bcc.n 80004d4 <CopyDataInit>
|
||||
80004e6: 4a09 ldr r2, [pc, #36] @ (800050c <LoopFillZerobss+0x1c>)
|
||||
80004e8: e002 b.n 80004f0 <LoopFillZerobss>
|
||||
|
||||
080004ea <FillZerobss>:
|
||||
80004ea: 2300 movs r3, #0
|
||||
80004ec: f842 3b04 str.w r3, [r2], #4
|
||||
|
||||
080004f0 <LoopFillZerobss>:
|
||||
80004f0: 4b07 ldr r3, [pc, #28] @ (8000510 <LoopFillZerobss+0x20>)
|
||||
80004f2: 429a cmp r2, r3
|
||||
80004f4: d3f9 bcc.n 80004ea <FillZerobss>
|
||||
80004f6: f7ff fe71 bl 80001dc <SystemInit>
|
||||
80004fa: f7ff fe45 bl 8000188 <main>
|
||||
80004fe: 4770 bx lr
|
||||
8000500: 0800061c stmdaeq r0, {r2, r3, r4, r9, sl}
|
||||
8000504: 20000000 andcs r0, r0, r0
|
||||
8000508: 20000008 andcs r0, r0, r8
|
||||
800050c: 20000008 andcs r0, r0, r8
|
||||
8000510: 200001bc @ <UNDEFINED> instruction: 0x200001bc
|
||||
|
||||
08000514 <ADC_IRQHandler>:
|
||||
8000514: e7fe b.n 8000514 <ADC_IRQHandler>
|
||||
...
|
||||
|
||||
08000518 <register_fini>:
|
||||
8000518: 4b02 ldr r3, [pc, #8] @ (8000524 <register_fini+0xc>)
|
||||
800051a: b113 cbz r3, 8000522 <register_fini+0xa>
|
||||
800051c: 4802 ldr r0, [pc, #8] @ (8000528 <register_fini+0x10>)
|
||||
800051e: f000 b81d b.w 800055c <atexit>
|
||||
8000522: 4770 bx lr
|
||||
8000524: 00000000 andeq r0, r0, r0
|
||||
8000528: 0800052d stmdaeq r0, {r0, r2, r3, r5, r8, sl}
|
||||
|
||||
0800052c <__libc_fini_array>:
|
||||
800052c: b538 push {r3, r4, r5, lr}
|
||||
800052e: 4d07 ldr r5, [pc, #28] @ (800054c <__libc_fini_array+0x20>)
|
||||
8000530: 4c07 ldr r4, [pc, #28] @ (8000550 <__libc_fini_array+0x24>)
|
||||
8000532: 1b2c subs r4, r5, r4
|
||||
8000534: 10a4 asrs r4, r4, #2
|
||||
8000536: d005 beq.n 8000544 <__libc_fini_array+0x18>
|
||||
8000538: 3c01 subs r4, #1
|
||||
800053a: f855 3d04 ldr.w r3, [r5, #-4]!
|
||||
800053e: 4798 blx r3
|
||||
8000540: 2c00 cmp r4, #0
|
||||
8000542: d1f9 bne.n 8000538 <__libc_fini_array+0xc>
|
||||
8000544: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
||||
8000548: f000 b854 b.w 80005f4 <_fini>
|
||||
800054c: 0800061c stmdaeq r0, {r2, r3, r4, r9, sl}
|
||||
8000550: 08000618 stmdaeq r0, {r3, r4, r9, sl}
|
||||
|
||||
08000554 <__retarget_lock_acquire_recursive>:
|
||||
8000554: 4770 bx lr
|
||||
8000556: bf00 nop
|
||||
|
||||
08000558 <__retarget_lock_release_recursive>:
|
||||
8000558: 4770 bx lr
|
||||
800055a: bf00 nop
|
||||
|
||||
0800055c <atexit>:
|
||||
800055c: 2300 movs r3, #0
|
||||
800055e: 4601 mov r1, r0
|
||||
8000560: 461a mov r2, r3
|
||||
8000562: 4618 mov r0, r3
|
||||
8000564: f000 b800 b.w 8000568 <__register_exitproc>
|
||||
|
||||
08000568 <__register_exitproc>:
|
||||
8000568: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
||||
800056c: 4d1b ldr r5, [pc, #108] @ (80005dc <__register_exitproc+0x74>)
|
||||
800056e: 4606 mov r6, r0
|
||||
8000570: 6828 ldr r0, [r5, #0]
|
||||
8000572: 4698 mov r8, r3
|
||||
8000574: 460f mov r7, r1
|
||||
8000576: 4691 mov r9, r2
|
||||
8000578: f7ff ffec bl 8000554 <__retarget_lock_acquire_recursive>
|
||||
800057c: 4b18 ldr r3, [pc, #96] @ (80005e0 <__register_exitproc+0x78>)
|
||||
800057e: 681c ldr r4, [r3, #0]
|
||||
8000580: b31c cbz r4, 80005ca <__register_exitproc+0x62>
|
||||
8000582: 6828 ldr r0, [r5, #0]
|
||||
8000584: 6865 ldr r5, [r4, #4]
|
||||
8000586: 2d1f cmp r5, #31
|
||||
8000588: dc22 bgt.n 80005d0 <__register_exitproc+0x68>
|
||||
800058a: b94e cbnz r6, 80005a0 <__register_exitproc+0x38>
|
||||
800058c: 1c6b adds r3, r5, #1
|
||||
800058e: 3502 adds r5, #2
|
||||
8000590: 6063 str r3, [r4, #4]
|
||||
8000592: f844 7025 str.w r7, [r4, r5, lsl #2]
|
||||
8000596: f7ff ffdf bl 8000558 <__retarget_lock_release_recursive>
|
||||
800059a: 2000 movs r0, #0
|
||||
800059c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
||||
80005a0: eb04 0185 add.w r1, r4, r5, lsl #2
|
||||
80005a4: 2301 movs r3, #1
|
||||
80005a6: f8c1 9088 str.w r9, [r1, #136] @ 0x88
|
||||
80005aa: f8d4 2188 ldr.w r2, [r4, #392] @ 0x188
|
||||
80005ae: 40ab lsls r3, r5
|
||||
80005b0: 431a orrs r2, r3
|
||||
80005b2: 2e02 cmp r6, #2
|
||||
80005b4: f8c4 2188 str.w r2, [r4, #392] @ 0x188
|
||||
80005b8: f8c1 8108 str.w r8, [r1, #264] @ 0x108
|
||||
80005bc: d1e6 bne.n 800058c <__register_exitproc+0x24>
|
||||
80005be: f8d4 218c ldr.w r2, [r4, #396] @ 0x18c
|
||||
80005c2: 431a orrs r2, r3
|
||||
80005c4: f8c4 218c str.w r2, [r4, #396] @ 0x18c
|
||||
80005c8: e7e0 b.n 800058c <__register_exitproc+0x24>
|
||||
80005ca: 4c06 ldr r4, [pc, #24] @ (80005e4 <__register_exitproc+0x7c>)
|
||||
80005cc: 601c str r4, [r3, #0]
|
||||
80005ce: e7d8 b.n 8000582 <__register_exitproc+0x1a>
|
||||
80005d0: f7ff ffc2 bl 8000558 <__retarget_lock_release_recursive>
|
||||
80005d4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
||||
80005d8: e7e0 b.n 800059c <__register_exitproc+0x34>
|
||||
80005da: bf00 nop
|
||||
80005dc: 20000004 andcs r0, r0, r4
|
||||
80005e0: 20000024 andcs r0, r0, r4, lsr #32
|
||||
80005e4: 2000002c andcs r0, r0, ip, lsr #32
|
||||
|
||||
080005e8 <_init>:
|
||||
80005e8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||||
80005ea: bf00 nop
|
||||
80005ec: bcf8 pop {r3, r4, r5, r6, r7}
|
||||
80005ee: bc08 pop {r3}
|
||||
80005f0: 469e mov lr, r3
|
||||
80005f2: 4770 bx lr
|
||||
|
||||
080005f4 <_fini>:
|
||||
80005f4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||||
80005f6: bf00 nop
|
||||
80005f8: bcf8 pop {r3, r4, r5, r6, r7}
|
||||
80005fa: bc08 pop {r3}
|
||||
80005fc: 469e mov lr, r3
|
||||
80005fe: 4770 bx lr
|
||||
|
||||
Disassembly of section .rodata:
|
||||
|
||||
08000600 <AHBPrescTable>:
|
||||
...
|
||||
8000608: 04030201 streq r0, [r3], #-513 @ 0xfffffdff
|
||||
800060c: 09080706 stmdbeq r8, {r1, r2, r8, r9, sl}
|
||||
|
||||
Disassembly of section .init_array:
|
||||
|
||||
08000610 <__init_array_start>:
|
||||
8000610: 08000519 stmdaeq r0, {r0, r3, r4, r8, sl}
|
||||
|
||||
08000614 <__frame_dummy_init_array_entry>:
|
||||
8000614: 080004ad stmdaeq r0, {r0, r2, r3, r5, r7, sl}
|
||||
|
||||
Disassembly of section .fini_array:
|
||||
|
||||
08000618 <__do_global_dtors_aux_fini_array_entry>:
|
||||
8000618: 08000485 stmdaeq r0, {r0, r2, r7, sl}
|
||||
|
||||
Disassembly of section .data:
|
||||
|
||||
20000000 <SystemCoreClock>:
|
||||
20000000: 0a037a00 beq 200de808 <_estack+0xae808>
|
||||
|
||||
20000004 <__atexit_recursive_mutex>:
|
||||
20000004: 20000028 andcs r0, r0, r8, lsr #32
|
||||
|
||||
Disassembly of section .ARM.attributes:
|
||||
|
||||
00000000 <.ARM.attributes>:
|
||||
0: 00002f41 andeq r2, r0, r1, asr #30
|
||||
4: 61656100 cmnvs r5, r0, lsl #2
|
||||
8: 01006962 tsteq r0, r2, ror #18
|
||||
c: 00000025 andeq r0, r0, r5, lsr #32
|
||||
10: 2d453705 stclcs 7, cr3, [r5, #-20] @ 0xffffffec
|
||||
14: 0d06004d stceq 0, cr0, [r6, #-308] @ 0xfffffecc
|
||||
18: 02094d07 andeq r4, r9, #448 @ 0x1c0
|
||||
1c: 0412060a ldreq r0, [r2], #-1546 @ 0xfffff9f6
|
||||
20: 01150114 tsteq r5, r4, lsl r1
|
||||
24: 01180317 tsteq r8, r7, lsl r3
|
||||
28: 011b011a tsteq fp, sl, lsl r1
|
||||
2c: 0122011c @ <UNDEFINED> instruction: 0x0122011c
|
||||
|
||||
Disassembly of section .comment:
|
||||
|
||||
00000000 <.comment>:
|
||||
0: 3a434347 bcc 10d0d24 <_Min_Stack_Size+0x10d0924>
|
||||
4: 72412820 subvc r2, r1, #32, 16 @ 0x200000
|
||||
8: 4e47206d cdpmi 0, 4, cr2, cr7, cr13, {3}
|
||||
c: 6f542055 svcvs 0x00542055
|
||||
10: 68636c6f stmdavs r3!, {r0, r1, r2, r3, r5, r6, sl, fp, sp, lr}^
|
||||
14: 206e6961 rsbcs r6, lr, r1, ror #18
|
||||
18: 322e3331 eorcc r3, lr, #-1006632960 @ 0xc4000000
|
||||
1c: 6c65722e sfmvs f7, 2, [r5], #-184 @ 0xffffff48
|
||||
20: 42282031 eormi r2, r8, #49 @ 0x31
|
||||
24: 646c6975 strbtvs r6, [ip], #-2421 @ 0xfffff68b
|
||||
28: 6d726120 ldfvse f6, [r2, #-128]! @ 0xffffff80
|
||||
2c: 2e33312d rsfcssp f3, f3, #5.0
|
||||
30: 20292937 eorcs r2, r9, r7, lsr r9
|
||||
34: 322e3331 eorcc r3, lr, #-1006632960 @ 0xc4000000
|
||||
38: 3220312e eorcc r3, r0, #-2147483637 @ 0x8000000b
|
||||
3c: 31333230 teqcc r3, r0, lsr r2
|
||||
40: 00393030 eorseq r3, r9, r0, lsr r0
|
||||
|
||||
Disassembly of section .debug_frame:
|
||||
|
||||
00000000 <.debug_frame>:
|
||||
0: 0000000c andeq r0, r0, ip
|
||||
4: ffffffff @ <UNDEFINED> instruction: 0xffffffff
|
||||
8: 7c020001 stcvc 0, cr0, [r2], {1}
|
||||
c: 000d0c0e andeq r0, sp, lr, lsl #24
|
||||
10: 0000000c andeq r0, r0, ip
|
||||
14: 00000000 andeq r0, r0, r0
|
||||
18: 08000518 stmdaeq r0, {r3, r4, r8, sl}
|
||||
1c: 00000014 andeq r0, r0, r4, lsl r0
|
||||
20: 00000038 andeq r0, r0, r8, lsr r0
|
||||
...
|
||||
2c: 000000c0 andeq r0, r0, r0, asr #1
|
||||
30: 84240e42 strthi r0, [r4], #-3650 @ 0xfffff1be
|
||||
34: 86088509 strhi r8, [r8], -r9, lsl #10
|
||||
38: 88068707 stmdahi r6, {r0, r1, r2, r8, r9, sl, pc}
|
||||
3c: 8a048905 bhi 122458 <_Min_Stack_Size+0x122058>
|
||||
40: 8e028b03 vmlahi.f64 d8, d2, d3
|
||||
44: 300e4301 andcc r4, lr, r1, lsl #6
|
||||
48: 240e0a76 strcs r0, [lr], #-2678 @ 0xfffff58a
|
||||
4c: cacbce42 bgt ff2f395c <_estack+0xdf2c395c>
|
||||
50: c6c7c8c9 strbgt ip, [r7], r9, asr #17
|
||||
54: 000ec4c5 andeq ip, lr, r5, asr #9
|
||||
58: 00000b42 andeq r0, r0, r2, asr #22
|
||||
5c: 0000000c andeq r0, r0, ip
|
||||
60: ffffffff @ <UNDEFINED> instruction: 0xffffffff
|
||||
64: 7c020001 stcvc 0, cr0, [r2], {1}
|
||||
68: 000d0c0e andeq r0, sp, lr, lsl #24
|
||||
6c: 00000020 andeq r0, r0, r0, lsr #32
|
||||
70: 0000005c andeq r0, r0, ip, asr r0
|
||||
74: 0800052c stmdaeq r0, {r2, r3, r5, r8, sl}
|
||||
78: 00000028 andeq r0, r0, r8, lsr #32
|
||||
7c: 83100e41 tsthi r0, #1040 @ 0x410
|
||||
80: 85038404 strhi r8, [r3, #-1028] @ 0xfffffbfc
|
||||
84: 4d018e02 stcmi 14, cr8, [r1, #-8]
|
||||
88: c3c4c5ce bicgt ip, r4, #864026624 @ 0x33800000
|
||||
8c: 0000000e andeq r0, r0, lr
|
||||
90: 0000000c andeq r0, r0, ip
|
||||
94: ffffffff @ <UNDEFINED> instruction: 0xffffffff
|
||||
98: 7c020001 stcvc 0, cr0, [r2], {1}
|
||||
9c: 000d0c0e andeq r0, sp, lr, lsl #24
|
||||
a0: 0000000c andeq r0, r0, ip
|
||||
a4: 00000090 muleq r0, r0, r0
|
||||
a8: 00000000 andeq r0, r0, r0
|
||||
ac: 00000002 andeq r0, r0, r2
|
||||
b0: 0000000c andeq r0, r0, ip
|
||||
b4: 00000090 muleq r0, r0, r0
|
||||
b8: 00000000 andeq r0, r0, r0
|
||||
bc: 00000002 andeq r0, r0, r2
|
||||
c0: 0000000c andeq r0, r0, ip
|
||||
c4: 00000090 muleq r0, r0, r0
|
||||
c8: 00000000 andeq r0, r0, r0
|
||||
cc: 00000002 andeq r0, r0, r2
|
||||
d0: 0000000c andeq r0, r0, ip
|
||||
d4: 00000090 muleq r0, r0, r0
|
||||
d8: 00000000 andeq r0, r0, r0
|
||||
dc: 00000002 andeq r0, r0, r2
|
||||
e0: 0000000c andeq r0, r0, ip
|
||||
e4: 00000090 muleq r0, r0, r0
|
||||
e8: 00000000 andeq r0, r0, r0
|
||||
ec: 00000002 andeq r0, r0, r2
|
||||
f0: 0000000c andeq r0, r0, ip
|
||||
f4: 00000090 muleq r0, r0, r0
|
||||
f8: 08000554 stmdaeq r0, {r2, r4, r6, r8, sl}
|
||||
fc: 00000002 andeq r0, r0, r2
|
||||
100: 0000000c andeq r0, r0, ip
|
||||
104: 00000090 muleq r0, r0, r0
|
||||
108: 00000000 andeq r0, r0, r0
|
||||
10c: 00000004 andeq r0, r0, r4
|
||||
110: 0000000c andeq r0, r0, ip
|
||||
114: 00000090 muleq r0, r0, r0
|
||||
118: 00000000 andeq r0, r0, r0
|
||||
11c: 00000004 andeq r0, r0, r4
|
||||
120: 0000000c andeq r0, r0, ip
|
||||
124: 00000090 muleq r0, r0, r0
|
||||
128: 00000000 andeq r0, r0, r0
|
||||
12c: 00000002 andeq r0, r0, r2
|
||||
130: 0000000c andeq r0, r0, ip
|
||||
134: 00000090 muleq r0, r0, r0
|
||||
138: 08000558 stmdaeq r0, {r3, r4, r6, r8, sl}
|
||||
13c: 00000002 andeq r0, r0, r2
|
||||
140: 0000000c andeq r0, r0, ip
|
||||
144: ffffffff @ <UNDEFINED> instruction: 0xffffffff
|
||||
148: 7c020001 stcvc 0, cr0, [r2], {1}
|
||||
14c: 000d0c0e andeq r0, sp, lr, lsl #24
|
||||
150: 0000000c andeq r0, r0, ip
|
||||
154: 00000140 andeq r0, r0, r0, asr #2
|
||||
158: 0800055c stmdaeq r0, {r2, r3, r4, r6, r8, sl}
|
||||
15c: 0000000c andeq r0, r0, ip
|
||||
160: 0000000c andeq r0, r0, ip
|
||||
164: ffffffff @ <UNDEFINED> instruction: 0xffffffff
|
||||
168: 7c020001 stcvc 0, cr0, [r2], {1}
|
||||
16c: 000d0c0e andeq r0, sp, lr, lsl #24
|
||||
170: 00000020 andeq r0, r0, r0, lsr #32
|
||||
174: 00000160 andeq r0, r0, r0, ror #2
|
||||
178: 08000568 stmdaeq r0, {r3, r5, r6, r8, sl}
|
||||
17c: 00000080 andeq r0, r0, r0, lsl #1
|
||||
180: 83200e42 @ <UNDEFINED> instruction: 0x83200e42
|
||||
184: 85078408 strhi r8, [r7, #-1032] @ 0xfffffbf8
|
||||
188: 87058606 strhi r8, [r5, -r6, lsl #12]
|
||||
18c: 89038804 stmdbhi r3, {r2, fp, pc}
|
||||
190: 00018e02 andeq r8, r1, r2, lsl #28
|
||||
@ -16,7 +16,7 @@ set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
|
||||
set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
|
||||
set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
|
||||
|
||||
set(shared_options "-mlittle-endian -mthumb -mcpu=cortex-m4 -mthumb-interwork -mfloat-abi=hard -mfpu=fpv4-sp-d16")
|
||||
set(shared_options "-Wall -Wextra -Os -mlittle-endian -mthumb -mcpu=cortex-m4 -mthumb-interwork -mfloat-abi=hard -mfpu=fpv4-sp-d16")
|
||||
set(CMAKE_C_FLAGS_INIT "${shared_options}" CACHE INTERNAL "Initial options for C compiler.")
|
||||
set(CMAKE_CXX_FLAGS_INIT "${shared_options}" CACHE INTERNAL "Initial options for C++ compiler.")
|
||||
set(CMAKE_EXE_LINKER_FLAGS_INIT "-Wl,--gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map" CACHE INTERNAL "Initial options for executable linker.")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user