From 65ca4d8ddbf85e61ff028b8293f18b515c5c798c Mon Sep 17 00:00:00 2001 From: Vasily Markov Date: Mon, 13 May 2024 15:02:23 +0300 Subject: [PATCH] fix --- app/app.c | 15 +- app/syscalls.c | 8 +- bsp/CMakeLists.txt | 4 +- bsp/bsp.c | 39 +- bsp/bsp.h | 3 + bsp/lwip/CMake1Lists.txt | 41 - bsp/lwip/ethernetif.c | 36 +- bsp/lwip/lwip.c | 4 +- bsp/lwip/lwipopts.h | 6 +- bsp/lwip/src/core/memp.c | 3 - bsp/lwip/src/core/timeouts.c | 1 - .../Legacy/stm32_hal_legacy.h | 3309 ----------------- .../lwip}/stm32f4xx_hal_def.h | 0 .../src => }/stm32f4xx_hal_eth.c | 5 +- .../inc => }/stm32f4xx_hal_eth.h | 0 bsp/ring_buffer.c | 58 + bsp/ring_buffer.h | 30 + bsp/stm32f4xx_it.c | 9 +- lib/CMakeLists.txt | 4 +- .../stm32f4x7_eth.h | 1890 ---------- .../stm32f4xx_hal_eth.h | 2241 ----------- .../stm32f4x7_eth.c | 2873 -------------- .../stm32f4xx_hal_eth.c | 2063 ---------- 23 files changed, 170 insertions(+), 12472 deletions(-) delete mode 100644 bsp/lwip/CMake1Lists.txt delete mode 100644 bsp/lwip/stm32f4_eth_periph/Legacy/stm32_hal_legacy.h rename {lib/inc/STM32F4xx_StdPeriph_Driver => bsp/lwip}/stm32f4xx_hal_def.h (100%) rename bsp/lwip/{stm32f4_eth_periph/src => }/stm32f4xx_hal_eth.c (99%) rename bsp/lwip/{stm32f4_eth_periph/inc => }/stm32f4xx_hal_eth.h (100%) create mode 100644 bsp/ring_buffer.c create mode 100644 bsp/ring_buffer.h delete mode 100644 lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.h delete mode 100644 lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.h delete mode 100644 lib/src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.c delete mode 100644 lib/src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.c diff --git a/app/app.c b/app/app.c index bea9fb4..ed92dac 100644 --- a/app/app.c +++ b/app/app.c @@ -3,10 +3,21 @@ void app() { init_LWIP(); - + static uint32_t loop_cnt = 0; + printf("FLASH->ACR: %d\r\n", FLASH->ACR); + printf("RCC->CFGR: %d\r\n", RCC->CFGR); + printf("RCC->CR): %d\r\n", RCC->CR); + printf("RCC->PLLCFGR: %d\r\n", RCC->PLLCFGR); + printf("RCC->APB1ENR: %d\r\n", RCC->APB1ENR); while(1) { process_LWIP(); - delay(400); + // if(loop_cnt == 10000) { + // GPIO_ToggleBits(GPIOB, GPIO_Pin_14); + // loop_cnt = 0; + // } + // loop_cnt++; + GPIO_ToggleBits(GPIOB, GPIO_Pin_14); + delay(1000); }; } diff --git a/app/syscalls.c b/app/syscalls.c index 4d97a3e..c7c1fc7 100644 --- a/app/syscalls.c +++ b/app/syscalls.c @@ -88,9 +88,13 @@ int _write(__attribute__((unused)) int file, char *ptr, int len) while(i < len) { while (USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); USART_SendData(USART2, *ptr++); - i++; + // ringbuf_uint8t* printf_buffer = get_printf_buffer(); + // if (!rb_is_full(printf_buffer)) { + // rb_put(printf_buffer, *ptr++); + // } + i++; } - + // USART2->CR1 |= USART_CR1_TXEIE; return len; } diff --git a/bsp/CMakeLists.txt b/bsp/CMakeLists.txt index 18545b6..c2be895 100644 --- a/bsp/CMakeLists.txt +++ b/bsp/CMakeLists.txt @@ -4,10 +4,11 @@ set(LWIP_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/lwip/src/core) add_library(bsp STATIC bsp.c + ring_buffer.c stm32f4xx_it.c lwip/lwip.c lwip/ethernetif.c - lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c + lwip/stm32f4xx_hal_eth.c ${LWIP_SOURCE_DIR}/api/err.c ${LWIP_SOURCE_DIR}/core/def.c ${LWIP_SOURCE_DIR}/core/init.c @@ -34,7 +35,6 @@ target_include_directories(bsp PRIVATE ${LWIP_INCLUDES} ${LWIP_INCLUDES}/lwip ${LWIP_INCLUDES}/netif - ${LWIP_INCLUDES}/stm32f4_eth_periph/inc ) target_link_libraries(bsp PUBLIC diff --git a/bsp/bsp.c b/bsp/bsp.c index b977fc8..4b30c2a 100644 --- a/bsp/bsp.c +++ b/bsp/bsp.c @@ -1,7 +1,16 @@ #include "misc.h" #include "bsp.h" + #define MAX_DELAY 0xFFFFFFFU +#define PRINTF_BUFFER_SIZE 128 + +static uint8_t printf_buffer[PRINTF_BUFFER_SIZE]; +static ringbuf_uint8t ring_buffer; + +ringbuf_uint8t* get_printf_buffer() { + return &ring_buffer; +} static lwip_status_t lwip_status = {.link_status = LINK_DOWN}; @@ -59,7 +68,11 @@ void usart_init() { usart.USART_BaudRate = 115200; usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(USART2, &usart); - USART_Cmd(USART2, ENABLE); + + // USART_ITConfig(USART2, USART_IT_TXE, ENABLE); + // NVIC_SetPriority(USART2_IRQn, 0); + // NVIC_EnableIRQ(USART2_IRQn); + USART_Cmd(USART2, ENABLE); } void tim_init() { @@ -86,21 +99,7 @@ void tim_init() { } void dma_init() { - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); - DMA_InitTypeDef dma; - dma.DMA_Channel = DMA_Channel_0; - dma.DMA_DIR = DMA_DIR_MemoryToMemory; - dma.DMA_PeripheralInc = DMA_PeripheralInc_Enable; - dma.DMA_MemoryInc = DMA_MemoryInc_Enable; - dma.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - dma.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - dma.DMA_Mode = DMA_Mode_Normal; - dma.DMA_Priority = DMA_Priority_Low; - dma.DMA_FIFOMode = DMA_FIFOMode_Enable; - dma.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - dma.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - dma.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_Init(DMA2_Stream0, &dma); + } void eth_init() { @@ -144,16 +143,20 @@ void eth_init() { void board_init() { uint32_t tick = SystemCoreClock/1000 - 1; - __enable_irq(); + FLASH_PrefetchBufferCmd(ENABLE); SysTick_Config(tick); NVIC_EnableIRQ(SysTick_IRQn); - gpio_init(); + gpio_init(); usart_init(); + // dma_init(); eth_init(); init_LWIP(); tim_init(); + rb_init(&ring_buffer, printf_buffer, PRINTF_BUFFER_SIZE); + printf("SysClk: %d\r\n", SystemCoreClock); printf("Controller is started...\r\n"); + } diff --git a/bsp/bsp.h b/bsp/bsp.h index 7e1d1fb..cb75ef5 100644 --- a/bsp/bsp.h +++ b/bsp/bsp.h @@ -7,7 +7,9 @@ #include "stm32f4xx_rcc.h" #include "stm32f4xx_dma.h" #include "stm32f4xx_tim.h" +#include "stm32f4xx_flash.h" #include "lwip/lwip.h" +#include "ring_buffer.h" typedef enum { LINK_DOWN, @@ -23,4 +25,5 @@ uint32_t getRegister(); uint32_t getSysTick(); void delay(uint32_t); lwip_status_t* get_lwip_status(); +ringbuf_uint8t* get_printf_buffer(); #endif diff --git a/bsp/lwip/CMake1Lists.txt b/bsp/lwip/CMake1Lists.txt deleted file mode 100644 index 5f840f0..0000000 --- a/bsp/lwip/CMake1Lists.txt +++ /dev/null @@ -1,41 +0,0 @@ -cmake_minimum_required(VERSION 3.5) - -project(lwip) - -set(LWIP_SOURCE_DIR ${CMAKE_SOURCE_DIR}/lwip) - -file(GLOB_RECURSE LWIP_SOURCES - ${LWIP_SOURCE_DIR}/src/core/*.c - ${LWIP_SOURCE_DIR}/src/netif/*.c -) -# message(${LWIP_SOURCES}) -add_library(lwip STATIC - lwip.c - # ethernetif.c - # stm32f4_eth_periph/src/stm32f4xx_hal_eth.c - # src/core/init.c - # src/core/init.c - # src/core/mem.c - # src/core/memp.c - # src/core/netif.c - # src/core/pbuf.c - # src/core/udp.c - # src/netif/ethernet.c - ${LWIP_SOURCES} -) - -# target_link_libraries(lwip PRIVATE stm32f4xx) - -set(DEVICE_FAMILY STM32F439xx) - -target_compile_definitions(lwip PUBLIC ${DEVICE_FAMILY}) - -target_include_directories(lwip PUBLIC - # ../bsp - # stm32f4_eth_periph/inc - # stm32f4_eth_periph/Legacy - src/include/lwip - src/include - system/ - ./ -) \ No newline at end of file diff --git a/bsp/lwip/ethernetif.c b/bsp/lwip/ethernetif.c index 6c064f5..7d2b882 100644 --- a/bsp/lwip/ethernetif.c +++ b/bsp/lwip/ethernetif.c @@ -132,7 +132,7 @@ static void low_level_init(struct netif *netif) printf("LAN8742A interface is RMII\r\r\n"); hal_eth_init_status = HAL_ETH_Init(&heth); - printf("Status: %d\r\n", hal_eth_init_status); + if (hal_eth_init_status == HAL_OK) { /* Set netif link flag */ @@ -182,7 +182,6 @@ static void low_level_init(struct netif *netif) /* Read Register Configuration */ HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , ®value); - printf("Link: %d\r\n", regvalue); #endif @@ -389,25 +388,26 @@ void check_link_status(struct netif* netif) { */ void ethernetif_input(struct netif *netif) { - // err_t err; - // struct pbuf *p; - // uint32_t regvalue = 0; - // /* move received packet into a new pbuf */ - // p = low_level_input(netif); - netif_set_link_callback(netif, ethernetif_update_config); + err_t err; + struct pbuf *p; + uint32_t regvalue = 0; + /* move received packet into a new pbuf */ + p = low_level_input(netif); + // if (p == NULL) printf("Null\r\n"); + // netif_set_link_callback(netif, ethernetif_update_config); check_link_status(netif); - // /* no packet could be read, silently ignore this */ - // if (p == NULL) return; + /* no packet could be read, silently ignore this */ + if (p == NULL) return; - // // /* entry point to the LwIP stack */ - // err = netif->input(p, netif); + /* entry point to the LwIP stack */ + err = netif->input(p, netif); - // if (err != ERR_OK) - // { - // LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - // pbuf_free(p); - // p = NULL; - // } + if (err != ERR_OK) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + pbuf_free(p); + p = NULL; + } } #if !LWIP_ARP diff --git a/bsp/lwip/lwip.c b/bsp/lwip/lwip.c index dec7c5c..cfc083c 100644 --- a/bsp/lwip/lwip.c +++ b/bsp/lwip/lwip.c @@ -5,8 +5,8 @@ #include "lwip/mem.h" #include "lwip/memp.h" #include "lwip/udp.h" -#include "netif/etharp.h" #include "lwip/timeouts.h" +#include "netif/etharp.h" #include "ethernetif.h" void Error_Handler(void); @@ -65,6 +65,6 @@ void init_LWIP(void) void process_LWIP() { ethernetif_input(&gnetif); - // sys_check_timeouts(); + sys_check_timeouts(); } diff --git a/bsp/lwip/lwipopts.h b/bsp/lwip/lwipopts.h index 7c2bdd8..9ee0cb7 100644 --- a/bsp/lwip/lwipopts.h +++ b/bsp/lwip/lwipopts.h @@ -88,7 +88,7 @@ /*----- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/ #define LWIP_ETHERNET 1 /*----- Default Value for LWIP_DHCP_CHECK_LINK_UP: 0 ---*/ -#define LWIP_DHCP_CHECK_LINK_UP 1 +#define LWIP_DHCP_CHECK_LINK_UP 0 /*----- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/ #define LWIP_DNS_SECURE 7 /*----- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS - 1))/TCP_MSS -----*/ @@ -150,6 +150,10 @@ #define LWIP_TCP 0 #define LWIP_NETIF_LINK_CALLBACK 1 + +#define PBUF_POOL_SIZE 8 + +#define PBUF_POOL_BUFSIZE 512 /* USER CODE END 1 */ #ifdef __cplusplus diff --git a/bsp/lwip/src/core/memp.c b/bsp/lwip/src/core/memp.c index 58fab1a..f22c7a0 100644 --- a/bsp/lwip/src/core/memp.c +++ b/bsp/lwip/src/core/memp.c @@ -416,7 +416,6 @@ do_memp_free_pool(const struct memp_desc* desc, void *mem) memp = (struct memp *)(void *)((u8_t*)mem - MEMP_SIZE); SYS_ARCH_PROTECT(old_level); - #if MEMP_OVERFLOW_CHECK == 1 memp_overflow_check_element_overflow(memp, desc); memp_overflow_check_element_underflow(memp, desc); @@ -485,9 +484,7 @@ memp_free(memp_t type, void *mem) #ifdef LWIP_HOOK_MEMP_AVAILABLE old_first = *memp_pools[type]->tab; #endif - do_memp_free_pool(memp_pools[type], mem); - #ifdef LWIP_HOOK_MEMP_AVAILABLE if (old_first == NULL) { LWIP_HOOK_MEMP_AVAILABLE(type); diff --git a/bsp/lwip/src/core/timeouts.c b/bsp/lwip/src/core/timeouts.c index 03affbb..80fed92 100644 --- a/bsp/lwip/src/core/timeouts.c +++ b/bsp/lwip/src/core/timeouts.c @@ -207,7 +207,6 @@ sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) { struct sys_timeo *timeout, *t; u32_t now, diff; - timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); if (timeout == NULL) { LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); diff --git a/bsp/lwip/stm32f4_eth_periph/Legacy/stm32_hal_legacy.h b/bsp/lwip/stm32f4_eth_periph/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 0ae9d0b..0000000 --- a/bsp/lwip/stm32f4_eth_periph/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3309 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7*/ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_def.h b/bsp/lwip/stm32f4xx_hal_def.h similarity index 100% rename from lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_def.h rename to bsp/lwip/stm32f4xx_hal_def.h diff --git a/bsp/lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c b/bsp/lwip/stm32f4xx_hal_eth.c similarity index 99% rename from bsp/lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c rename to bsp/lwip/stm32f4xx_hal_eth.c index eba8b85..42087bf 100644 --- a/bsp/lwip/stm32f4_eth_periph/src/stm32f4xx_hal_eth.c +++ b/bsp/lwip/stm32f4xx_hal_eth.c @@ -181,7 +181,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) uint32_t hclk = 60000000U; uint32_t tickstart = 0U; uint32_t err = ETH_SUCCESS; - + printf("Ethernet init\r\n"); /* Check the ETH peripheral state */ if(heth == NULL) { @@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { /* In case of write timeout */ err = ETH_ERROR; - + printf("mac timeout\r\n"); /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); @@ -1602,7 +1602,6 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) ETH_MACInitTypeDef macinit; ETH_DMAInitTypeDef dmainit; uint32_t tmpreg1 = 0U; - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ { /* Set Ethernet duplex mode to Full-duplex */ diff --git a/bsp/lwip/stm32f4_eth_periph/inc/stm32f4xx_hal_eth.h b/bsp/lwip/stm32f4xx_hal_eth.h similarity index 100% rename from bsp/lwip/stm32f4_eth_periph/inc/stm32f4xx_hal_eth.h rename to bsp/lwip/stm32f4xx_hal_eth.h diff --git a/bsp/ring_buffer.c b/bsp/ring_buffer.c new file mode 100644 index 0000000..7fc8c34 --- /dev/null +++ b/bsp/ring_buffer.c @@ -0,0 +1,58 @@ +#include "ring_buffer.h" + +///////////////////////// UINT8_T RING BUFFER ////////////////////////////// + +//initializes the given ringbuffer with the supplied array and its length +inline void rb_init(ringbuf_uint8t *rb, uint8_t *array, unsigned char length) +{ + rb->buf = array; + rb->length = length; + rb->head = rb->tail = 0; + // zero out buffer + for (uint8_t idx=0; idx < length; ++idx){ + rb->buf[idx] = 0; + } +} + +//returns boolean true if the ringbuffer is empty, false otherwise +inline unsigned char rb_is_empty(ringbuf_uint8t *rb) +{ + return (rb->head == rb->tail); +} + +//returns boolean true if the ringbuffer is full, false otherwise +inline unsigned char rb_is_full(ringbuf_uint8t *rb) +{ + return (((rb->tail + 1) % rb->length) == rb->head); +} + +//consumes an element from the buffer +//returns NULL if buffer is empty or a pointer to the array element otherwise +inline uint8_t* rb_get(ringbuf_uint8t *rb) +{ + uint8_t *ret; + if (rb->head == rb->tail) + return 0; + else + { + ret = rb->buf + rb->head; //index into the array at head pointer + rb->head = (rb->head + 1) % rb->length; //move head pointer forward one element (with wraparound) + return ret; + } +} + +//puts an element into the buffer +//returns 0 if buffer is full, otherwise returns 1 +inline unsigned char rb_put(ringbuf_uint8t *rb, uint8_t c) +{ + char newtail; + newtail = (rb->tail + 1) % rb->length; //calculate where the new tail would be + if (newtail == rb->head) //if the new tail would make the buffer look empty, buffer is full + return 0; + else + { + rb->buf[rb->tail] = c; //store the data + rb->tail = newtail; //move the tail pointer forward (with wraparound) + return 1; + } +} diff --git a/bsp/ring_buffer.h b/bsp/ring_buffer.h new file mode 100644 index 0000000..ed6f9cb --- /dev/null +++ b/bsp/ring_buffer.h @@ -0,0 +1,30 @@ +#ifndef RING_BUFFER_H +#define RING_BUFFER_H + +#include + +///////////////////////// UINT8_T RING BUFFER ////////////////////////////// +typedef struct { + uint8_t *buf; //points to data array + unsigned char length; //length of data array + unsigned char head, tail; //producer and consumer indices +} ringbuf_uint8t; + +//initializes the given ringbuffer with the supplied array and its length +void rb_init(ringbuf_uint8t *rb, uint8_t *array, unsigned char length); + +//returns boolean true if the ringbuffer is empty, false otherwise +unsigned char rb_is_empty(ringbuf_uint8t *rb); + +//returns boolean true if the ringbuffer is full, false otherwise +unsigned char rb_is_full(ringbuf_uint8t *rb); + +//consumes an element from the buffer +//returns NULL if buffer is empty or a pointer to the array element otherwise +uint8_t* rb_get(ringbuf_uint8t *rb); + +//puts an element into the buffer +//returns 0 if buffer is full, otherwise returns 1 +unsigned char rb_put(ringbuf_uint8t *rb, uint8_t c); + +#endif \ No newline at end of file diff --git a/bsp/stm32f4xx_it.c b/bsp/stm32f4xx_it.c index f6ced44..c8e9b2a 100644 --- a/bsp/stm32f4xx_it.c +++ b/bsp/stm32f4xx_it.c @@ -1,4 +1,5 @@ #include "stm32f4xx_it.h" +#include "ring_buffer.h" static volatile uint32_t sysTick = 0; @@ -16,7 +17,13 @@ void TIM7_IRQHandler() void USART2_IRQHandler() { - + ringbuf_uint8t* printf_buffer = get_printf_buffer(); + while(!rb_is_empty(printf_buffer)) { + while (USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, (uint16_t)(rb_get(printf_buffer))); + } + USART1->CR1 &= ~USART_CR1_TXEIE; + GPIO_ToggleBits(GPIOB, GPIO_Pin_7); } void SysTick_Handler(void) diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt index 3e536fd..a07f4a5 100644 --- a/lib/CMakeLists.txt +++ b/lib/CMakeLists.txt @@ -20,7 +20,7 @@ add_library(stm32f4xx STATIC # src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dcmi.c src/STM32F4xx_StdPeriph_Driver/stm32f4xx_dma.c # src/STM32F4xx_StdPeriph_Driver/stm32f4xx_exti.c - # src/STM32F4xx_StdPeriph_Driver/stm32f4xx_flash.c + src/STM32F4xx_StdPeriph_Driver/stm32f4xx_flash.c # src/STM32F4xx_StdPeriph_Driver/stm32f4xx_fsmc.c src/STM32F4xx_StdPeriph_Driver/stm32f4xx_gpio.c # src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hash.c @@ -52,7 +52,7 @@ target_include_directories(stm32f4xx PUBLIC target_compile_definitions(stm32f4xx PUBLIC USE_STDPERIPH_DRIVER) target_compile_definitions(stm32f4xx PUBLIC ${DEVICE_FAMILY}) target_compile_definitions(stm32f4xx PUBLIC HSE_VALUE=8000000) -target_compile_definitions(stm32f4xx PUBLIC SYSTEM_CORE_CLOCK=180000000) +target_compile_definitions(stm32f4xx PUBLIC SYSTEM_CORE_CLOCK=160000000) target_compile_definitions(stm32f4xx PUBLIC USE_STM324x7I_EVAL) target_compile_options(stm32f4xx PRIVATE -nostartfiles) diff --git a/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.h b/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.h deleted file mode 100644 index f19e4fe..0000000 --- a/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.h +++ /dev/null @@ -1,1890 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4x7_eth.h - * @author MCD Application Team - * @version V1.1.0 - * @date 31-July-2013 - * @brief This file contains all the functions prototypes for the Ethernet - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4x7_ETH_H -#define __STM32F4x7_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4x7_eth_conf.h" - -/** @addtogroup STM32F4x7_ETH_Driver - * @{ - */ - -/** @defgroup ETH_Exported_Types - * @{ - */ - -/** - * @brief ETH MAC Init structure definition - * @note The user should not configure all the ETH_InitTypeDef structure's fields. - * By calling the ETH_StructInit function the structure�s fields are set to their default values. - * Only the parameters that will be set to a non-default value should be configured. - */ -typedef struct { -/** - * @brief / * MAC - */ - uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_watchdog */ - - uint32_t ETH_Jabber; /*!< Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps - This parameter can be a value of @ref ETH_Speed */ - - uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode) - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering) - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ - - uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ - - uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the - transmit control frame */ - - uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - -/** - * @brief / * DMA - */ - - uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t ETH_TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ - - uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration - This parameter can be a value of @ref ETH_DMA_Arbitration */ -}ETH_InitTypeDef; - -/**--------------------------------------------------------------------------**/ -/** - * @brief DMA descriptors types - */ -/**--------------------------------------------------------------------------**/ - -/** - * @brief ETH DMA Descriptors data structure definition - */ -typedef struct { - __IO uint32_t Status; /*!< Status */ - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ -/* Enhanced ETHERNET DMA PTP Descriptors */ -#ifdef USE_ENHANCED_DMA_DESCRIPTORS - uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */ - uint32_t Reserved1; /* Reserved */ - uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */ - uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */ -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ -} ETH_DMADESCTypeDef; - - -typedef struct{ - u32 length; - u32 buffer; - __IO ETH_DMADESCTypeDef *descriptor; -}FrameTypeDef; - - -typedef struct { - __IO ETH_DMADESCTypeDef *FS_Rx_Desc; /*!< First Segment Rx Desc */ - __IO ETH_DMADESCTypeDef *LS_Rx_Desc; /*!< Last Segment Rx Desc */ - __IO uint32_t Seg_Count; /*!< Segment count */ -} ETH_DMA_Rx_Frame_infos; - - -/** - * @} - */ - -/** @defgroup ETH_Exported_Constants - * @{ - */ - -/**--------------------------------------------------------------------------**/ -/** - * @brief ETH Frames defines - */ -/**--------------------------------------------------------------------------**/ - -/** @defgroup ENET_Buffers_setting - * @{ - */ -#define ETH_MAX_PACKET_SIZE 1524 /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC 4 /*!< Ethernet CRC */ -#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ -#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ -#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ -#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ - - /* Ethernet driver receive buffers are organized in a chained linked-list, when - an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - to the driver receive buffers memory. - - Depending on the size of the received ethernet packet and the size of - each ethernet driver receive buffer, the received packet can take one or more - ethernet driver receive buffer. - - In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE - and the total count of the driver receive buffers ETH_RXBUFNB. - - The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ -#ifndef ETH_RXBUFNB - #define ETH_RXBUFNB 5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#endif - - - /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an ethernet packet is transmitted, Tx-DMA will transfer the packet from the - driver transmit buffers memory to the TxFIFO. - - Depending on the size of the Ethernet packet to be transmitted and the size of - each ethernet driver transmit buffer, the packet to be transmitted can take - one or more ethernet driver transmit buffer. - - In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE - and the total count of the driver transmit buffers ETH_TXBUFNB. - - The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ -#ifndef ETH_TXBUFNB - #define ETH_TXBUFNB 5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ -#endif - -#define ETH_DMARxDesc_FrameLengthShift 16 - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet DMA descriptors registers bits definition - */ -/**--------------------------------------------------------------------------**/ - -/** -@code - DMA Tx Desciptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -@endcode -*/ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ -#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ -#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ -#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ -#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ -#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ -#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ -#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ -#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ -#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ -#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ -#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ -#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ -#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ -#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ -#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ -#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ -#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ -#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ -#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - - /*--------------------------------------------------------------------------------------------- - TDES6 | Transmit Time Stamp Low [31:0] | - ----------------------------------------------------------------------------------------------- - TDES7 | Transmit Time Stamp High [31:0] | - ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTxDesc_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTxDesc_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */ - -/** - * @} - */ - - -/** @defgroup DMA_Rx_descriptor - * @{ - */ - -/** -@code - DMA Rx Descriptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -@endcode -*/ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ -#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ -#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ -#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ -#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ -#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ -#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ -#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ -#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ -#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ -#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ -#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ -#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - RDES4 | Reserved[31:15] | Extended Status [14:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES5 | Reserved[31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES6 | Receive Time Stamp Low [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES7 | Receive Time Stamp High [31:0] | - --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ -#define ETH_DMAPTPRxDesc_PTPV ((uint32_t)0x00002000) /* PTP Version */ -#define ETH_DMAPTPRxDesc_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ -#define ETH_DMAPTPRxDesc_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ - #define ETH_DMAPTPRxDesc_PTPMT_Sync ((uint32_t)0x00000100) /* SYNC message (all clock types) */ - #define ETH_DMAPTPRxDesc_PTPMT_FollowUp ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ - #define ETH_DMAPTPRxDesc_PTPMT_DelayReq ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ - #define ETH_DMAPTPRxDesc_PTPMT_DelayResp ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ - #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRxDesc_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ -#define ETH_DMAPTPRxDesc_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ -#define ETH_DMAPTPRxDesc_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRxDesc_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ -#define ETH_DMAPTPRxDesc_IPHE ((uint32_t)0x00000008) /* IP Header Error */ -#define ETH_DMAPTPRxDesc_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ - #define ETH_DMAPTPRxDesc_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRxDesc_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRxDesc_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ -#define ETH_DMAPTPRxDesc_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ -#define ETH_DMAPTPRxDesc_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */ - - -/**--------------------------------------------------------------------------**/ -/** - * @brief Description of common PHY registers - */ -/**--------------------------------------------------------------------------**/ - -/** - * @} - */ - -/** @defgroup PHY_Read_write_Timeouts - * @{ - */ -#define PHY_READ_TO ((uint32_t)0x0004FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) - -/** - * @} - */ - -/** @defgroup PHY_Register_address - * @{ - */ -#define PHY_BCR 0 /*!< Transceiver Basic Control Register */ -#define PHY_BSR 1 /*!< Transceiver Basic Status Register */ - -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) -#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ - ((REG) == PHY_BSR) || \ - ((REG) == PHY_SR)) -/** - * @} - */ - -/** @defgroup PHY_basic_Control_register - * @{ - */ -#define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -/** - * @} - */ - -/** @defgroup PHY_basic_status_register - * @{ - */ -#define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/** - * @} - */ - -/**--------------------------------------------------------------------------**/ -/** - * @brief MAC defines - */ -/**--------------------------------------------------------------------------**/ - -/** @defgroup ETH_AutoNegotiation - * @{ - */ -#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) -#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ - ((CMD) == ETH_AutoNegotiation_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_watchdog - * @{ - */ -#define ETH_Watchdog_Enable ((uint32_t)0x00000000) -#define ETH_Watchdog_Disable ((uint32_t)0x00800000) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ - ((CMD) == ETH_Watchdog_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Jabber - * @{ - */ -#define ETH_Jabber_Enable ((uint32_t)0x00000000) -#define ETH_Jabber_Disable ((uint32_t)0x00400000) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ - ((CMD) == ETH_Jabber_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap - * @{ - */ -#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ - ((GAP) == ETH_InterFrameGap_88Bit) || \ - ((GAP) == ETH_InterFrameGap_80Bit) || \ - ((GAP) == ETH_InterFrameGap_72Bit) || \ - ((GAP) == ETH_InterFrameGap_64Bit) || \ - ((GAP) == ETH_InterFrameGap_56Bit) || \ - ((GAP) == ETH_InterFrameGap_48Bit) || \ - ((GAP) == ETH_InterFrameGap_40Bit)) - -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense - * @{ - */ -#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) -#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ - ((CMD) == ETH_CarrierSense_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Speed - * @{ - */ -#define ETH_Speed_10M ((uint32_t)0x00000000) -#define ETH_Speed_100M ((uint32_t)0x00004000) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ - ((SPEED) == ETH_Speed_100M)) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Own - * @{ - */ -#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) -#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ - ((CMD) == ETH_ReceiveOwn_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode - * @{ - */ -#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) -#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ - ((CMD) == ETH_LoopbackMode_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Duplex_Mode - * @{ - */ -#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) -#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ - ((MODE) == ETH_Mode_HalfDuplex)) - -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload - * @{ - */ -#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) -#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ - ((CMD) == ETH_ChecksumOffload_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission - * @{ - */ -#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) -#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ - ((CMD) == ETH_RetryTransmission_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip - * @{ - */ -#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) -#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ - ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit - * @{ - */ -#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) -#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) -#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) -#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ - ((LIMIT) == ETH_BackOffLimit_8) || \ - ((LIMIT) == ETH_BackOffLimit_4) || \ - ((LIMIT) == ETH_BackOffLimit_1)) - -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check - * @{ - */ -#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) -#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ - ((CMD) == ETH_DeferralCheck_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Receive_All - * @{ - */ -#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) -#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ - ((CMD) == ETH_ReceiveAll_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter - * @{ - */ -#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) -#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) -#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ - ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ - ((CMD) == ETH_SourceAddrFilter_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames - * @{ - */ -#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ - ((PASS) == ETH_PassControlFrames_ForwardAll) || \ - ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) - -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception - * @{ - */ -#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) -#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ - ((CMD) == ETH_BroadcastFramesReception_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter - * @{ - */ -#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) -#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ - ((FILTER) == ETH_DestinationAddrFilter_Inverse)) - -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode - * @{ - */ -#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) -#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ - ((CMD) == ETH_PromiscuousMode_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter - * @{ - */ -#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) -#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) -#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) -#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ - ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ - ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ - ((FILTER) == ETH_MulticastFramesFilter_None)) - - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter - * @{ - */ -#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) -#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) -#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ - ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ - ((FILTER) == ETH_UnicastFramesFilter_Perfect)) - -/** - * @} - */ - -/** @defgroup ETH_Pause_Time - * @{ - */ -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) - -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause - * @{ - */ -#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) -#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ - ((CMD) == ETH_ZeroQuantaPause_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold - * @{ - */ -#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ -#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ -#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ -#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ - ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ - ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ - ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect - * @{ - */ -#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) -#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ - ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control - * @{ - */ -#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) -#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ - ((CMD) == ETH_ReceiveFlowControl_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control - * @{ - */ -#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) -#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ - ((CMD) == ETH_TransmitFlowControl_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison - * @{ - */ -#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) -#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ - ((COMPARISON) == ETH_VLANTagComparison_16Bit)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) - -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags - * @{ - */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts - * @{ - */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ -#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses - * @{ - */ -#define ETH_MAC_Address0 ((uint32_t)0x00000000) -#define ETH_MAC_Address1 ((uint32_t)0x00000008) -#define ETH_MAC_Address2 ((uint32_t)0x00000010) -#define ETH_MAC_Address3 ((uint32_t)0x00000018) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ - ((ADDRESS) == ETH_MAC_Address1) || \ - ((ADDRESS) == ETH_MAC_Address2) || \ - ((ADDRESS) == ETH_MAC_Address3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ - ((ADDRESS) == ETH_MAC_Address2) || \ - ((ADDRESS) == ETH_MAC_Address3)) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames - * @{ - */ -#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) -#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ - ((FILTER) == ETH_MAC_AddressFilter_DA)) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes - * @{ - */ -#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ - ((MASK) == ETH_MAC_AddressMask_Byte5) || \ - ((MASK) == ETH_MAC_AddressMask_Byte4) || \ - ((MASK) == ETH_MAC_AddressMask_Byte3) || \ - ((MASK) == ETH_MAC_AddressMask_Byte2) || \ - ((MASK) == ETH_MAC_AddressMask_Byte1)) - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet DMA Descriptors defines - */ -/**--------------------------------------------------------------------------**/ -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_flags - * @{ - */ -#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ - ((FLAG) == ETH_DMATxDesc_IC) || \ - ((FLAG) == ETH_DMATxDesc_LS) || \ - ((FLAG) == ETH_DMATxDesc_FS) || \ - ((FLAG) == ETH_DMATxDesc_DC) || \ - ((FLAG) == ETH_DMATxDesc_DP) || \ - ((FLAG) == ETH_DMATxDesc_TTSE) || \ - ((FLAG) == ETH_DMATxDesc_TER) || \ - ((FLAG) == ETH_DMATxDesc_TCH) || \ - ((FLAG) == ETH_DMATxDesc_TTSS) || \ - ((FLAG) == ETH_DMATxDesc_IHE) || \ - ((FLAG) == ETH_DMATxDesc_ES) || \ - ((FLAG) == ETH_DMATxDesc_JT) || \ - ((FLAG) == ETH_DMATxDesc_FF) || \ - ((FLAG) == ETH_DMATxDesc_PCE) || \ - ((FLAG) == ETH_DMATxDesc_LCA) || \ - ((FLAG) == ETH_DMATxDesc_NC) || \ - ((FLAG) == ETH_DMATxDesc_LCO) || \ - ((FLAG) == ETH_DMATxDesc_EC) || \ - ((FLAG) == ETH_DMATxDesc_VF) || \ - ((FLAG) == ETH_DMATxDesc_CC) || \ - ((FLAG) == ETH_DMATxDesc_ED) || \ - ((FLAG) == ETH_DMATxDesc_UF) || \ - ((FLAG) == ETH_DMATxDesc_DB)) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment - * @{ - */ -#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ -#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ - ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control - * @{ - */ -#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ -#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ -#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ - ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ - ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ - ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) -/** - * @brief ETH DMA Tx Desciptor buffer size - */ -#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_flags - * @{ - */ -#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ - ((FLAG) == ETH_DMARxDesc_AFM) || \ - ((FLAG) == ETH_DMARxDesc_ES) || \ - ((FLAG) == ETH_DMARxDesc_DE) || \ - ((FLAG) == ETH_DMARxDesc_SAF) || \ - ((FLAG) == ETH_DMARxDesc_LE) || \ - ((FLAG) == ETH_DMARxDesc_OE) || \ - ((FLAG) == ETH_DMARxDesc_VLAN) || \ - ((FLAG) == ETH_DMARxDesc_FS) || \ - ((FLAG) == ETH_DMARxDesc_LS) || \ - ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ - ((FLAG) == ETH_DMARxDesc_LC) || \ - ((FLAG) == ETH_DMARxDesc_FT) || \ - ((FLAG) == ETH_DMARxDesc_RWT) || \ - ((FLAG) == ETH_DMARxDesc_RE) || \ - ((FLAG) == ETH_DMARxDesc_DBE) || \ - ((FLAG) == ETH_DMARxDesc_CE) || \ - ((FLAG) == ETH_DMARxDesc_MAMPCE)) - -/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/ -#define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \ - ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \ - ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \ - ((FLAG) == ETH_DMAPTPRxDesc_IPPT)) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers_ - * @{ - */ -#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ - ((BUFFER) == ETH_DMARxDesc_Buffer2)) - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet DMA defines - */ -/**--------------------------------------------------------------------------**/ -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame - * @{ - */ -#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) -#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ - ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward - * @{ - */ -#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) -#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ - ((CMD) == ETH_ReceiveStoreForward_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame - * @{ - */ -#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) -#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ - ((CMD) == ETH_FlushReceivedFrame_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward - * @{ - */ -#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) -#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ - ((CMD) == ETH_TransmitStoreForward_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control - * @{ - */ -#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ - ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames - * @{ - */ -#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) -#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ - ((CMD) == ETH_ForwardErrorFrames_Disable)) -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames - * @{ - */ -#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) -#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ - ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control - * @{ - */ -#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ - ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ - ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ - ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate - * @{ - */ -#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) -#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ - ((CMD) == ETH_SecondFrameOperate_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats - * @{ - */ -#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) -#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ - ((CMD) == ETH_AddressAlignedBeats_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst - * @{ - */ -#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) -#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ - ((CMD) == ETH_FixedBurst_Disable)) - -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length - * @{ - */ -#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ - -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ - ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) - -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length - * @{ - */ -#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ - -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ - ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) -/** - * @brief ETH DMA Descriptor SkipLength - */ -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration - * @{ - */ -#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) -#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) -#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) -#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ - ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ - ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ - ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ - ((RATIO) == ETH_DMAArbitration_RxPriorTx)) -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags - * @{ - */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ -#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ - -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ - ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts - * @{ - */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ - -#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) - -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state_ - * @{ - */ -#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ -#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state_ - * @{ - */ -#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ -#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ -#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow_ - * @{ - */ -#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ - ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet PMT defines - */ -/**--------------------------------------------------------------------------**/ -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags - * @{ - */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet MMC defines - */ -/**--------------------------------------------------------------------------**/ -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts - * @{ - */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ - -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts - * @{ - */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ -#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ - ((IT) != 0x00)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -/** - * @} - */ - -/** @defgroup ETH_MMC_Registers - * @{ - */ -#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ -#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ -#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ -#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ -#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ -#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ -#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ -#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ - -/** - * @brief ETH MMC registers - */ -#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ - ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ - ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ - ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ - ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ - ((REG) == ETH_MMCRGUFCR)) - -/**--------------------------------------------------------------------------**/ -/** - * @brief Ethernet PTP defines - */ -/**--------------------------------------------------------------------------**/ -/** - * @} - */ - -/** @defgroup ETH_PTP_time_update_method - * @{ - */ -#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ -#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ -#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ - ((UPDATE) == ETH_PTP_CoarseUpdate)) - -/** - * @} - */ - - -/** @defgroup ETH_PTP_Flags - * @{ - */ -#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ -#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ -#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ -#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ - -#define ETH_PTP_FLAG_TSTTR ((uint32_t)0x10000002) /* Time stamp target time reached */ -#define ETH_PTP_FLAG_TSSO ((uint32_t)0x10000001) /* Time stamp seconds overflow */ - -#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ - ((FLAG) == ETH_PTP_FLAG_TSITE) || \ - ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ - ((FLAG) == ETH_PTP_FLAG_TSSTI) || \ - ((FLAG) == ETH_PTP_FLAG_TSTTR) || \ - ((FLAG) == ETH_PTP_FLAG_TSSO)) - -/** - * @brief ETH PTP subsecond increment - */ -#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) - -/** - * @} - */ - - -/** @defgroup ETH_PTP_time_sign - * @{ - */ -#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ -#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ -#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ - ((SIGN) == ETH_PTP_NegativeTime)) - -/** - * @brief ETH PTP time stamp low update - */ -#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) - -/** - * @brief ETH PTP registers - */ -#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ -#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ -#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ -#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ -#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ -#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ -#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ -#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ -#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ - -#define ETH_PTPTSSR ((uint32_t)0x00000728) /* PTP TSSR register */ - -#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ - ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ - ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ - ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ - ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) - -/** - * @brief ETHERNET PTP clock - */ -#define ETH_PTP_OrdinaryClock ((uint32_t)0x00000000) /* Ordinary Clock */ -#define ETH_PTP_BoundaryClock ((uint32_t)0x00010000) /* Boundary Clock */ -#define ETH_PTP_EndToEndTransparentClock ((uint32_t)0x00020000) /* End To End Transparent Clock */ -#define ETH_PTP_PeerToPeerTransparentClock ((uint32_t)0x00030000) /* Peer To Peer Transparent Clock */ - -#define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \ - ((CLOCK) == ETH_PTP_BoundaryClock) || \ - ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \ - ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock)) -/** - * @brief ETHERNET snapshot - */ -#define ETH_PTP_SnapshotMasterMessage ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTP_SnapshotEventMessage ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ -#define ETH_PTP_SnapshotIPV4Frames ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTP_SnapshotIPV6Frames ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTP_SnapshotPTPOverEthernetFrames ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTP_SnapshotAllReceivedFrames ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ - -#define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \ - ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \ - ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \ - ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \ - ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \ - ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames)) - -/** - * @} - */ -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) - -/* ETHERNET MACCR register Mask */ -#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) - -/* ETHERNET MACFCR register Mask */ -#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) - - -/* ETHERNET DMAOMR register Mask */ -#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) - - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET errors */ -#define ETH_ERROR ((uint32_t)0) -#define ETH_SUCCESS ((uint32_t)1) - -/** - * @} - */ - -/** @defgroup ETH_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions - * @{ - */ -void ETH_DeInit(void); -uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress); -void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); -void ETH_SoftwareReset(void); -FlagStatus ETH_GetSoftwareResetStatus(void); -void ETH_Start(void); -void ETH_Stop(void); -uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc); - - -#ifdef USE_ENHANCED_DMA_DESCRIPTORS - void ETH_EnhancedDescriptorCmd(FunctionalState NewState); -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ - -/** - * @brief PHY - */ -uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); -uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); -uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); - -/** - * @brief MAC - */ -void ETH_MACTransmissionCmd(FunctionalState NewState); -void ETH_MACReceptionCmd(FunctionalState NewState); -FlagStatus ETH_GetFlowControlBusyStatus(void); -void ETH_InitiatePauseControlFrame(void); -void ETH_BackPressureActivationCmd(FunctionalState NewState); -FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); -ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); -void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); -void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); -void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); -void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); -void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); -void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); - -/** - * @brief DMA Tx/Rx descriptors - */ -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -uint32_t ETH_CheckFrameReceived(void); -uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength); -FrameTypeDef ETH_Get_Received_Frame(void); -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); -#ifdef USE_ENHANCED_DMA_DESCRIPTORS - FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag); -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); -void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); -FrameTypeDef ETH_Get_Received_Frame_interrupt(void); -/** - * @brief DMA - */ -FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); -void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); -ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); -void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); -uint32_t ETH_GetTransmitProcessState(void); -uint32_t ETH_GetReceiveProcessState(void); -void ETH_FlushTransmitFIFO(void); -FlagStatus ETH_GetFlushTransmitFIFOStatus(void); -void ETH_DMATransmissionCmd(FunctionalState NewState); -void ETH_DMAReceptionCmd(FunctionalState NewState); -void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); -FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); -uint32_t ETH_GetRxOverflowMissedFrameCounter(void); -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); -uint32_t ETH_GetCurrentTxDescStartAddress(void); -uint32_t ETH_GetCurrentRxDescStartAddress(void); -uint32_t ETH_GetCurrentTxBufferAddress(void); -uint32_t ETH_GetCurrentRxBufferAddress(void); -void ETH_ResumeDMATransmission(void); -void ETH_ResumeDMAReception(void); -void ETH_SetReceiveWatchdogTimer(uint8_t Value); - - -/** - * @brief PMT - */ -void ETH_ResetWakeUpFrameFilterRegisterPointer(void); -void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); -void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); -FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); -void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); -void ETH_MagicPacketDetectionCmd(FunctionalState NewState); -void ETH_PowerDownCmd(FunctionalState NewState); - -/** - * @brief MMC - */ -void ETH_MMCCounterFullPreset(void); -void ETH_MMCCounterHalfPreset(void); -void ETH_MMCCounterFreezeCmd(FunctionalState NewState); -void ETH_MMCResetOnReadCmd(FunctionalState NewState); -void ETH_MMCCounterRolloverCmd(FunctionalState NewState); -void ETH_MMCCountersReset(void); -void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); -ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); -uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4x7_ETH_H */ -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.h b/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.h deleted file mode 100644 index fd7c958..0000000 --- a/lib/inc/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.h +++ /dev/null @@ -1,2241 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_eth.h - * @author MCD Application Team - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_ETH_H -#define __STM32F4xx_HAL_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" -#include "stddef.h" -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ - ((IT) != 0x00U)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - -/** - * @} - */ - - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY 0x00000001U - -/* ETHERNET Errors */ -#define ETH_SUCCESS 0U -#define ETH_ERROR 1U - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U - -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK 0xFF20810FU - -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U - -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - /** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* LAN8742A_PHY_ADDRESS Address*/ -#define LAN8742A_PHY_ADDRESS 0U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -#define PHY_ISFR ((uint16_t)0x000BU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition - */ - -typedef struct -{ - uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. - This parameter can be a value of @ref ETH_Speed */ - - uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint16_t PhyAddress; /*!< Ethernet PHY address. - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. - This parameter can be a value of @ref ETH_Rx_Mode */ - - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. - This parameter can be a value of @ref ETH_Checksum_Mode */ - - uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. - This parameter can be a value of @ref ETH_Media_Interface */ - -} ETH_InitTypeDef; - - - /** - * @brief ETH MAC Configuration Structure definition - */ - -typedef struct -{ - uint32_t Watchdog; /*!< Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_Watchdog */ - - uint32_t Jabber; /*!< Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode. - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode). - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t BackOffLimit; /*!< Selects the BackOff limit value. - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ - - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ - - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ - - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame. - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address). - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering. - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - -} ETH_MACInitTypeDef; - -/** - * @brief ETH DMA Configuration Structure definition - */ - -typedef struct -{ - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. - This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ - - uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. - This parameter can be a value of @ref ETH_DMA_Arbitration */ -} ETH_DMAInitTypeDef; - - -/** - * @brief ETH DMA Descriptors data structure definition - */ - -typedef struct -{ - __IO uint32_t Status; /*!< Status */ - - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - - /*!< Enhanced ETHERNET DMA PTP Descriptors */ - uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ - - uint32_t Reserved1; /*!< Reserved */ - - uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ - - uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ - -} ETH_DMADescTypeDef; - -/** - * @brief Received Frame Informations structure definition - */ -typedef struct -{ - ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ - - ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ - - uint32_t SegCount; /*!< Segment count */ - - uint32_t length; /*!< Frame length */ - - uint32_t buffer; /*!< Frame buffer */ - -} ETH_DMARxFrameInfos; - -/** - * @brief ETH Handle Structure definition - */ - -typedef struct -{ - ETH_TypeDef *Instance; /*!< Register base address */ - - ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ - - uint32_t LinkStatus; /*!< Ethernet link status */ - - ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ - - ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ - - ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ - - __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ - - HAL_LockTypeDef Lock; /*!< ETH Lock */ - -} ETH_HandleTypeDef; - - /** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ETH_Exported_Constants ETH Exported Constants - * @{ - */ - -/** @defgroup ETH_Buffers_setting ETH Buffers setting - * @{ - */ -#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC 4U /*!< Ethernet CRC */ -#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ - - /* Ethernet driver receive buffers are organized in a chained linked-list, when - an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - to the driver receive buffers memory. - - Depending on the size of the received ethernet packet and the size of - each ethernet driver receive buffer, the received packet can take one or more - ethernet driver receive buffer. - - In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE - and the total count of the driver receive buffers ETH_RXBUFNB. - - The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ -#ifndef ETH_RXBUFNB - #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#endif - - - /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an ethernet packet is transmitted, Tx-DMA will transfer the packet from the - driver transmit buffers memory to the TxFIFO. - - Depending on the size of the Ethernet packet to be transmitted and the size of - each ethernet driver transmit buffer, the packet to be transmitted can take - one or more ethernet driver transmit buffer. - - In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE - and the total count of the driver transmit buffers ETH_TXBUFNB. - - The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ -#ifndef ETH_TXBUFNB - #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ -#endif - - /** - * @} - */ - -/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor - * @{ - */ - -/* - DMA Tx Descriptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ -#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ -#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ -#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ -#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ -#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ -#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ -#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ -#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ -#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ - - /*--------------------------------------------------------------------------------------------- - TDES6 | Transmit Time Stamp Low [31:0] | - ----------------------------------------------------------------------------------------------- - TDES7 | Transmit Time Stamp High [31:0] | - ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ - -/** - * @} - */ -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor - * @{ - */ - -/* - DMA Rx Descriptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ -#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ -#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ -#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ -#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - RDES4 | Reserved[31:15] | Extended Status [14:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES5 | Reserved[31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES6 | Receive Time Stamp Low [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES7 | Receive Time Stamp High [31:0] | - --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ - #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ - #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ -/** - * @} - */ - /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation - * @{ - */ -#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U -#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U - -/** - * @} - */ -/** @defgroup ETH_Speed ETH Speed - * @{ - */ -#define ETH_SPEED_10M 0x00000000U -#define ETH_SPEED_100M 0x00004000U - -/** - * @} - */ -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode - * @{ - */ -#define ETH_MODE_FULLDUPLEX 0x00000800U -#define ETH_MODE_HALFDUPLEX 0x00000000U -/** - * @} - */ -/** @defgroup ETH_Rx_Mode ETH Rx Mode - * @{ - */ -#define ETH_RXPOLLING_MODE 0x00000000U -#define ETH_RXINTERRUPT_MODE 0x00000001U -/** - * @} - */ - -/** @defgroup ETH_Checksum_Mode ETH Checksum Mode - * @{ - */ -#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U -#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U -/** - * @} - */ - -/** @defgroup ETH_Media_Interface ETH Media Interface - * @{ - */ -#define ETH_MEDIA_INTERFACE_MII 0x00000000U -#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) -/** - * @} - */ - -/** @defgroup ETH_Watchdog ETH Watchdog - * @{ - */ -#define ETH_WATCHDOG_ENABLE 0x00000000U -#define ETH_WATCHDOG_DISABLE 0x00800000U -/** - * @} - */ - -/** @defgroup ETH_Jabber ETH Jabber - * @{ - */ -#define ETH_JABBER_ENABLE 0x00000000U -#define ETH_JABBER_DISABLE 0x00400000U -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap - * @{ - */ -#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense ETH Carrier Sense - * @{ - */ -#define ETH_CARRIERSENCE_ENABLE 0x00000000U -#define ETH_CARRIERSENCE_DISABLE 0x00010000U -/** - * @} - */ - -/** @defgroup ETH_Receive_Own ETH Receive Own - * @{ - */ -#define ETH_RECEIVEOWN_ENABLE 0x00000000U -#define ETH_RECEIVEOWN_DISABLE 0x00002000U -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode - * @{ - */ -#define ETH_LOOPBACKMODE_ENABLE 0x00001000U -#define ETH_LOOPBACKMODE_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload ETH Checksum Offload - * @{ - */ -#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U -#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission ETH Retry Transmission - * @{ - */ -#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U -#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip - * @{ - */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit - * @{ - */ -#define ETH_BACKOFFLIMIT_10 0x00000000U -#define ETH_BACKOFFLIMIT_8 0x00000020U -#define ETH_BACKOFFLIMIT_4 0x00000040U -#define ETH_BACKOFFLIMIT_1 0x00000060U -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check ETH Deferral Check - * @{ - */ -#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U -#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Receive_All ETH Receive All - * @{ - */ -#define ETH_RECEIVEALL_ENABLE 0x80000000U -#define ETH_RECEIVEAll_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter - * @{ - */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U -#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames - * @{ - */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception - * @{ - */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter - * @{ - */ -#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U -#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode - * @{ - */ -#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U -#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter - * @{ - */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U -#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U -#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter - * @{ - */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U -#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U -#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause - * @{ - */ -#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U -#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold - * @{ - */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect - * @{ - */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control - * @{ - */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U -#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control - * @{ - */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U -#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison - * @{ - */ -#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U -#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses ETH MAC addresses - * @{ - */ -#define ETH_MAC_ADDRESS0 0x00000000U -#define ETH_MAC_ADDRESS1 0x00000008U -#define ETH_MAC_ADDRESS2 0x00000010U -#define ETH_MAC_ADDRESS3 0x00000018U -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA - * @{ - */ -#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U -#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes - * @{ - */ -#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame - * @{ - */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward - * @{ - */ -#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U -#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame - * @{ - */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U -#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward - * @{ - */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U -#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control - * @{ - */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames - * @{ - */ -#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U -#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames - * @{ - */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control - * @{ - */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate - * @{ - */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U -#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats - * @{ - */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U -#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst ETH Fixed Burst - * @{ - */ -#define ETH_FIXEDBURST_ENABLE 0x00010000U -#define ETH_FIXEDBURST_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length - * @{ - */ -#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length - * @{ - */ -#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format - * @{ - */ -#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U -#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration - * @{ - */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U -#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment - * @{ - */ -#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control - * @{ - */ -#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers - * @{ - */ -#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags ETH PMT Flags - * @{ - */ -#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts - * @{ - */ -#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts - * @{ - */ -#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags ETH MAC Flags - * @{ - */ -#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags ETH DMA Flags - * @{ - */ -#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ -#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ -#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts - * @{ - */ -#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts - * @{ - */ -#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ -#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state - * @{ - */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state - * @{ - */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow ETH DMA overflow - * @{ - */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ -/** - * @} - */ - -/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP - * @{ - */ -#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Macros ETH Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** @brief Reset ETH handle state - * @param __HANDLE__ specifies the ETH handle. - * @retval None - */ -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) - -/** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param __HANDLE__ ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param __HANDLE__ ETH Handle - * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param __HANDLE__ ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of ETHERNET MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __OVERFLOW__ specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__ ETH Handle - * @param __VALUE__ DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param __HANDLE__ ETH Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) - -/** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) - -/** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) - -/** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) - -/** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) - -/** - * @brief Resets the MMC Counters. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) - -/** - * @brief Enables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Disables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Enables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) - -/** - * @brief Enables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enable event on ETH External event line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disable event on ETH External event line - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Get flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - }while(0U) - -/** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - }while(0U) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); - -/** - * @} - */ -/* IO operation functions ****************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_ETH_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.c b/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.c deleted file mode 100644 index 677d087..0000000 --- a/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4x7_eth.c +++ /dev/null @@ -1,2873 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4x7_eth.c - * @author MCD Application Team - * @version V1.1.0 - * @date 31-July-2013 - * @brief This file is the low level driver for STM32F4x7xx Ethernet Controller. - * This driver does not include low level functions for PTP time-stamp. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4x7_eth.h" -#include "stm32f4xx_rcc.h" -#include - -/** @addtogroup STM32F4x7_ETH_Driver - * @brief ETH driver modules -* @{ -*/ - -/** @defgroup ETH_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup ETH_Private_Defines -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup ETH_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup ETH_Private_Variables -* @{ -*/ - -#if defined (__CC_ARM) /*!< ARM Compiler */ -__align(4) -ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */ -__align(4) -ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */ -__align(4) -uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */ -__align(4) -uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */ - -#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma data_alignment=4 -ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */ -#pragma data_alignment=4 -ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */ -#pragma data_alignment=4 -uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */ -#pragma data_alignment=4 -uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */ - -#elif defined (__GNUC__) /*!< GNU Compiler */ -ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Rx DMA Descriptor */ -ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Tx DMA Descriptor */ -uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Receive Buffer */ -uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Transmit Buffer */ - -#elif defined (__TASKING__) /*!< TASKING Compiler */ -__align(4) -ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */ -__align(4) -ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */ -__align(4) -uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */ -__align(4) -uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */ - -#endif /* __CC_ARM */ - - -/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ -__IO ETH_DMADESCTypeDef *DMATxDescToSet; -__IO ETH_DMADESCTypeDef *DMARxDescToGet; - - -/* Structure used to hold the last received packet descriptors info */ -ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor; -__IO ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos; -__IO uint32_t Frame_Rx_index; - - -/** -* @} -*/ - -/** @defgroup ETH_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - -/** @defgroup ETH_Private_Functions -* @{ -*/ - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void ETH_Delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = nCount; index != 0; index--) - { - } -} -#endif /* USE_Delay*/ - - -/******************************************************************************/ -/* Global ETH MAC/DMA functions */ -/******************************************************************************/ - -/** - * @brief De-initializes the ETHERNET peripheral registers to their default reset values. - * @param None - * @retval None - */ -void ETH_DeInit(void) -{ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); -} - -/** - * @brief Fills each ETH_InitStruct member with its default value. - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized. - * @retval None - */ -void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) -{ - /* ETH_InitStruct members default value */ - /*------------------------ MAC Configuration ---------------------------*/ - - /* PHY Auto-negotiation enabled */ - ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; - /* MAC watchdog enabled: cuts off long frame */ - ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; - /* MAC Jabber enabled in Half-duplex mode */ - ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; - /* Ethernet interframe gap set to 96 bits */ - ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; - /* Carrier Sense Enabled in Half-Duplex mode */ - ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; - /* PHY speed configured to 100Mbit/s */ - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - /* Receive own Frames in Half-Duplex mode enabled */ - ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; - /* MAC MII loopback disabled */ - ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; - /* Full-Duplex mode selected */ - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - /* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */ - ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; - /* Retry Transmission enabled for half-duplex mode */ - ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; - /* Automatic PAD/CRC strip disabled*/ - ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - /* half-duplex mode retransmission Backoff time_limit = 10 slot times*/ - ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; - /* half-duplex mode Deferral check disabled */ - ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; - /* Receive all frames disabled */ - ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; - /* Source address filtering (on the optional MAC addresses) disabled */ - ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; - /* Do not forward control frames that do not pass the address filtering */ - ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; - /* Disable reception of Broadcast frames */ - ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; - /* Normal Destination address filtering (not reverse addressing) */ - ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; - /* Promiscuous address filtering mode disabled */ - ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; - /* Perfect address filtering for multicast addresses */ - ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; - /* Perfect address filtering for unicast addresses */ - ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; - /* Initialize hash table high and low regs */ - ETH_InitStruct->ETH_HashTableHigh = 0x0; - ETH_InitStruct->ETH_HashTableLow = 0x0; - /* Flow control config (flow control disabled)*/ - ETH_InitStruct->ETH_PauseTime = 0x0; - ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; - ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; - ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; - ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; - ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; - /* VLANtag config (VLAN field not checked) */ - ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; - ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; - - /*---------------------- DMA Configuration -------------------------------*/ - - /* Drops frames with with TCP/IP checksum errors */ - ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; - /* Store and forward mode enabled for receive */ - ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - /* Flush received frame that created FIFO overflow */ - ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; - /* Store and forward mode enabled for transmit */ - ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - /* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */ - ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; - /* Disable forwarding frames with errors (short frames, CRC,...)*/ - ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - /* Disable undersized good frames */ - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - /* Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled) */ - ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; - /* Disable Operate on second frame (transmit a second frame to FIFO without - waiting status of previous frame*/ - ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; - /* DMA works on 32-bit aligned start source and destinations addresses */ - ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - /* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */ - ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable; - /* DMA transfer max burst length = 32 beats = 32 x 32bits */ - ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; - ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; - /* DMA Ring mode skip length = 0 */ - ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; - /* Equal priority (round-robin) between transmit and receive DMA engines */ - ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; -} - -/** - * @brief Initializes the ETHERNET peripheral according to the specified - * parameters in the ETH_InitStruct . - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains - * the configuration information for the specified ETHERNET peripheral. - * @param PHYAddress: external PHY address - * @retval ETH_ERROR: Ethernet initialization failed - * ETH_SUCCESS: Ethernet successfully initialized - */ -uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) -{ - uint32_t RegValue = 0, tmpreg = 0; - __IO uint32_t i = 0; - RCC_ClocksTypeDef rcc_clocks; - uint32_t hclk = 60000000; - __IO uint32_t timeout = 0, err = ETH_SUCCESS; - /* Check the parameters */ - /* MAC --------------------------*/ - assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); - assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); - assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); - assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); - assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); - assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); - /* DMA --------------------------*/ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); - /*-------------------------------- MAC Config ------------------------------*/ - /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= MACMIIAR_CR_MASK; - /* Get hclk frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - hclk = rcc_clocks.HCLK_Frequency; - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000)&&(hclk < 35000000)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000)&&(hclk < 60000000)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000)&&(hclk < 100000000)) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000)&&(hclk < 150000000)) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */ - { - /* CSR Clock Range between 150-168 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - ETH->MACMIIAR = (uint32_t)tmpreg; - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) - { - /* Return ERROR in case of write timeout */ - err = ETH_ERROR; - goto error; - } - - /* Delay to assure PHY reset */ - _eth_delay_(PHY_RESET_DELAY); - - if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) - { - /* We wait for linked status...*/ - do - { - timeout++; - } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); - - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - err = ETH_ERROR; - goto error; - } - - /* Reset Timeout counter */ - timeout = 0; - /* Enable Auto-Negotiation */ - if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) - { - /* Return ERROR in case of write timeout */ - err = ETH_ERROR; - } - - /* Wait until the auto-negotiation will be completed */ - do - { - timeout++; - } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); - - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - err = ETH_ERROR; - goto error; - } - - /* Reset Timeout counter */ - timeout = 0; - /* Read the result of the auto-negotiation */ - RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((RegValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - } - else - { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if(RegValue & PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - } - } - else - { - if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) | - (uint16_t)(ETH_InitStruct->ETH_Speed >> 1)))) - { - /* Return ERROR in case of write timeout */ - err = ETH_ERROR; - } - /* Delay to assure PHY configuration */ - _eth_delay_(PHY_CONFIG_DELAY); - } -error: - if (err == ETH_ERROR) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - - /* Set Ethernet speed to 100M */ - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - } - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = ETH->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH_Watchdog value */ - /* Set the JD: bit according to ETH_Jabber value */ - /* Set the IFG bit according to ETH_InterFrameGap value */ - /* Set the DCRS bit according to ETH_CarrierSense value */ - /* Set the FES bit according to ETH_Speed value */ - /* Set the DO bit according to ETH_ReceiveOwn value */ - /* Set the LM bit according to ETH_LoopbackMode value */ - /* Set the DM bit according to ETH_Mode value */ - /* Set the IPCO bit according to ETH_ChecksumOffload value */ - /* Set the DR bit according to ETH_RetryTransmission value */ - /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH_BackOffLimit value */ - /* Set the DC bit according to ETH_DeferralCheck value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | - ETH_InitStruct->ETH_Jabber | - ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | - ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | - ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); - /* Write to ETHERNET MACCR */ - ETH->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH_ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ - /* Set the PCF bit according to ETH_PassControlFrames value */ - /* Set the DBF bit according to ETH_BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ - /* Set the PR bit according to ETH_PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | - ETH_InitStruct->ETH_SourceAddrFilter | - ETH_InitStruct->ETH_PassControlFrames | - ETH_InitStruct->ETH_BroadcastFramesReception | - ETH_InitStruct->ETH_DestinationAddrFilter | - ETH_InitStruct->ETH_PromiscuousMode | - ETH_InitStruct->ETH_MulticastFramesFilter | - ETH_InitStruct->ETH_UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACFFR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = ETH->MACFCR; - /* Clear xx bits */ - tmpreg &= MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH_PauseTime value */ - /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ - /* Set the PLT bit according to ETH_PauseLowThreshold value */ - /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH_ReceiveFlowControl value */ - /* Set the TFE bit according to ETH_TransmitFlowControl value */ - tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | - ETH_InitStruct->ETH_UnicastPauseFrameDetect | - ETH_InitStruct->ETH_ReceiveFlowControl | - ETH_InitStruct->ETH_TransmitFlowControl); - /* Write to ETHERNET MACFCR */ - ETH->MACFCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACFCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACFCR = tmpreg; - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - /* Set the ETV bit according to ETH_VLANTagComparison value */ - /* Set the VL bit according to ETH_VLANTagIdentifier value */ - ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | - ETH_InitStruct->ETH_VLANTagIdentifier); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACVLANTR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACVLANTR = tmpreg; - - /*-------------------------------- DMA Config ------------------------------*/ - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - - /* Get the ETHERNET DMAOMR value */ - tmpreg = ETH->DMAOMR; - /* Clear xx bits */ - tmpreg &= DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH_ReceiveStoreForward value */ - /* Set the DFF bit according to ETH_FlushReceivedFrame value */ - /* Set the TSF bit according to ETH_TransmitStoreForward value */ - /* Set the TTC bit according to ETH_TransmitThresholdControl value */ - /* Set the FEF bit according to ETH_ForwardErrorFrames value */ - /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH_SecondFrameOperate value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | - ETH_InitStruct->ETH_FlushReceivedFrame | - ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | - ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); - /* Write to ETHERNET DMAOMR */ - ETH->DMAOMR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->DMAOMR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->DMAOMR = tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - /* Set the AAL bit according to ETH_AddressAlignedBeats value */ - /* Set the FB bit according to ETH_FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ - /* Set the DSL bit according to ETH_DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH_DMAArbitration value */ - ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | - ETH_InitStruct->ETH_FixedBurst | - ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - ETH_InitStruct->ETH_TxDMABurstLength | - (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | - ETH_InitStruct->ETH_DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->DMABMR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->DMABMR = tmpreg; - -#ifdef USE_ENHANCED_DMA_DESCRIPTORS - /* Enable the Enhanced DMA descriptors */ - ETH->DMABMR |= ETH_DMABMR_EDE; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->DMABMR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->DMABMR = tmpreg; -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ - - /* Return Ethernet configuration success */ - if(err == ETH_SUCCESS) - { - /* Return Ethernet configuration success */ - return ETH_SUCCESS; - } - else /* Auto-negotiation failed */ - { - /* Return Ethernet error */ - return ETH_ERROR; - } -} - -/** - * @brief Enables ENET MAC and DMA reception/transmission - * @param None - * @retval None - */ -void ETH_Start(void) -{ - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionCmd(ENABLE); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionCmd(ENABLE); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(); - - /* Start DMA transmission */ - ETH_DMATransmissionCmd(ENABLE); - - /* Start DMA reception */ - ETH_DMAReceptionCmd(ENABLE); -} - -/** - * @brief Disables ENET MAC and DMA reception/transmission - * @param None - * @retval None - */ -void ETH_Stop(void) -{ - /* Stop DMA transmission */ - ETH_DMATransmissionCmd(DISABLE); - - /* Stop DMA reception */ - ETH_DMAReceptionCmd(DISABLE); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionCmd(DISABLE); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionCmd(DISABLE); -} - -/** - * @brief Enables or disables the MAC transmission. - * @param NewState: new state of the MAC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACTransmissionCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC transmission */ - ETH->MACCR |= ETH_MACCR_TE; - } - else - { - /* Disable the MAC transmission */ - ETH->MACCR &= ~ETH_MACCR_TE; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACCR = tmpreg; -} - -/** - * @brief Enables or disables the MAC reception. - * @param NewState: new state of the MAC reception. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACReceptionCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC reception */ - ETH->MACCR |= ETH_MACCR_RE; - } - else - { - /* Disable the MAC reception */ - ETH->MACCR &= ~ETH_MACCR_RE; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACCR = tmpreg; -} - -/** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param None - * @retval The new state of flow control busy status bit (SET or RESET). - */ -FlagStatus ETH_GetFlowControlBusyStatus(void) -{ - FlagStatus bitstatus = RESET; - /* The Flow Control register should not be written to until this bit is cleared */ - if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param None - * @retval None - */ -void ETH_InitiatePauseControlFrame(void) -{ - __IO uint32_t tmpreg = 0; - /* When Set In full duplex MAC initiates pause control frame */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACFCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACFCR = tmpreg; -} - -/** - * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). - * @param NewState: new state of the MAC BackPressure operation activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_BackPressureActivationCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Activate the MAC BackPressure operation */ - /* In Half duplex: during backpressure, when the MAC receives a new frame, - the transmitter starts sending a JAM pattern resulting in a collision */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; - } - else - { - /* Desactivate the MAC BackPressure operation */ - ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACFCR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACFCR = tmpreg; -} - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param ETH_MAC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The new state of ETHERNET MAC flag (SET or RESET). - */ -FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); - if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. - * @param ETH_MAC_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt - * @arg ETH_MAC_IT_MMCR : MMC receive interrupt - * @arg ETH_MAC_IT_MMC : MMC interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval The new state of ETHERNET MAC interrupt (SET or RESET). - */ -ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); - if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Enables or disables the specified ETHERNET MAC interrupts. - * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @param NewState: new state of the specified ETHERNET MAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MAC interrupts */ - ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); - } - else - { - /* Disable the selected ETHERNET MAC interrupts */ - ETH->MACIMR |= ETH_MAC_IT; - } -} - -/** - * @brief Configures the selected MAC address. - * @param MacAddr: The MAC address to configure. - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Addr: Pointer on MAC address buffer data (6 bytes). - * @retval None - */ -void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - - /* Calculate the selected MAC address high register */ - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; - /* Load the selected MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; - /* Calculate the selected MAC address low register */ - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - - /* Load the selected MAC address low register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; -} - -/** - * @brief Get the selected MAC address. - * @param MacAddr: The MAC address to return. - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Addr: Pointer on MAC address buffer data (6 bytes). - * @retval None - */ -void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - - /* Get the selected MAC address high register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - - /* Calculate the selected MAC address buffer */ - Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); - Addr[4] = (tmpreg & (uint8_t)0xFF); - /* Load the selected MAC address low register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)); - /* Calculate the selected MAC address buffer */ - Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); - Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); - Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); - Addr[0] = (tmpreg & (uint8_t)0xFF); -} - -/** - * @brief Enables or disables the Address filter module uses the specified - * ETHERNET MAC address for perfect filtering - * @param MacAddr: specifies the ETHERNET MAC address to be used for perfect filtering. - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param NewState: new state of the specified ETHERNET MAC address use. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; - } - else - { - /* Disable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - _eth_delay_(ETH_REG_WRITE_DELAY); - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; -} - -/** - * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Filter: specifies the used frame received field for comparison - * This parameter can be one of the following values: - * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the - * SA fields of the received frame. - * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the - * DA fields of the received frame. - * @retval None - */ -void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); - - if (Filter != ETH_MAC_AddressFilter_DA) - { - /* The selected ETHERNET MAC address is used to compare with the SA fields of the - received frame. */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; - } - else - { - /* The selected ETHERNET MAC address is used to compare with the DA fields of the - received frame. */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - _eth_delay_(ETH_REG_WRITE_DELAY); - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; -} - -/** - * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param MaskByte: specifies the used address bytes for comparison - * This parameter can be any combination of the following values: - * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. - * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. - * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. - * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. - * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. - * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. - * @retval None - */ -void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); - - /* Clear MBC bits in the selected MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - _eth_delay_(ETH_REG_WRITE_DELAY); - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; - - /* Set the selected Filter mask bytes */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - _eth_delay_(ETH_REG_WRITE_DELAY); - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; -} - -/******************************************************************************/ -/* DMA Descriptors functions */ -/******************************************************************************/ -/** - * @brief This function should be called to get the received frame (to be used - * with polling method only). - * @param none - * @retval Structure of type FrameTypeDef - */ -FrameTypeDef ETH_Get_Received_Frame(void) -{ - uint32_t framelength = 0; - FrameTypeDef frame = {0,0,0}; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; - frame.length = framelength; - - /* Get the address of the first frame descriptor and the buffer start address */ - frame.descriptor = DMA_RX_FRAME_infos->FS_Rx_Desc; - frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr; - - /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ - /* Chained Mode */ - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - - /* Return Frame */ - return (frame); -} - -/** - * @brief This function should be called when a frame is received using DMA - * Receive interrupt, it allows scanning of Rx descriptors to get the - * the receive frame (should be used with interrupt mode only) - * @param None - * @retval Structure of type FrameTypeDef - */ -FrameTypeDef ETH_Get_Received_Frame_interrupt(void) -{ - FrameTypeDef frame={0,0,0}; - __IO uint32_t descriptor_scan_counter = 0; - - /* scan descriptors owned by CPU */ - while (((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET)&& - (descriptor_scan_counterStatus & ETH_DMARxDesc_FS) != (uint32_t)RESET)&& - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)) - { - DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet; - DMA_RX_FRAME_infos->Seg_Count = 1; - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - - /* check if intermediate segment */ - else if (((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)&& - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)) - { - (DMA_RX_FRAME_infos->Seg_Count) ++; - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - - /* should be last segment */ - else - { - /* last segment */ - DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet; - - (DMA_RX_FRAME_infos->Seg_Count)++; - - /* first segment is last segment */ - if ((DMA_RX_FRAME_infos->Seg_Count)==1) - DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - frame.length = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; - - /* Get the address of the buffer start address */ - /* Check if more than one segment in the frame */ - if (DMA_RX_FRAME_infos->Seg_Count >1) - { - frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr; - } - else - { - frame.buffer = DMARxDescToGet->Buffer1Addr; - } - - frame.descriptor = DMA_RX_FRAME_infos->FS_Rx_Desc; - - /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - - /* Return Frame */ - return (frame); - } - } - return (frame); -} - -/** - * @brief Prepares DMA Tx descriptors to transmit an ethernet frame - * @param FrameLength : length of the frame to send - * @retval error status - */ -uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength) -{ - uint32_t buf_count =0, size=0,i=0; - __IO ETH_DMADESCTypeDef *DMATxDesc; - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET) - { - /* Return ERROR: OWN bit set */ - return ETH_ERROR; - } - - DMATxDesc = DMATxDescToSet; - - if (FrameLength > ETH_TX_BUF_SIZE) - { - buf_count = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength%ETH_TX_BUF_SIZE) buf_count++; - } - else buf_count =1; - - if (buf_count ==1) - { - /*set LAST and FIRST segment */ - DMATxDesc->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS; - /* Set frame size */ - DMATxDesc->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMATxDesc->Status |= ETH_DMATxDesc_OWN; - DMATxDesc= (ETH_DMADESCTypeDef *)(DMATxDesc->Buffer2NextDescAddr); - } - else - { - for (i=0; i< buf_count; i++) - { - /* Clear FIRST and LAST segment bits */ - DMATxDesc->Status &= ~(ETH_DMATxDesc_FS | ETH_DMATxDesc_LS); - - if (i==0) - { - /* Setting the first segment bit */ - DMATxDesc->Status |= ETH_DMATxDesc_FS; - } - - /* Program size */ - DMATxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1); - - if (i== (buf_count-1)) - { - /* Setting the last segment bit */ - DMATxDesc->Status |= ETH_DMATxDesc_LS; - size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE; - DMATxDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1); - } - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMATxDesc->Status |= ETH_DMATxDesc_OWN; - - DMATxDesc = (ETH_DMADESCTypeDef *)(DMATxDesc->Buffer2NextDescAddr); - } - } - - DMATxDescToSet = DMATxDesc; - - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - ETH->DMATPDR = 0; - } - - /* Return SUCCESS */ - return ETH_SUCCESS; -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param DMARxDescTab: Pointer on the first Rx desc list - * @param RxBuff: Pointer on the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list - * @retval None - */ -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARxDesc_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE; - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - /* Set Receive Descriptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; - - DMA_RX_FRAME_infos = &RX_Frame_Descriptor; - -} - -/** - * @brief This function polls for a frame reception - * @param None - * @retval Returns 1 when a frame is received, 0 if none. - */ -uint32_t ETH_CheckFrameReceived(void) -{ - /* check if last segment */ - if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET)) - { - DMA_RX_FRAME_infos->Seg_Count++; - if (DMA_RX_FRAME_infos->Seg_Count == 1) - { - DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet; - } - DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet; - return 1; - } - - /* check if first segment */ - else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&& - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)) - { - DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet; - DMA_RX_FRAME_infos->LS_Rx_Desc = NULL; - DMA_RX_FRAME_infos->Seg_Count = 1; - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - - /* check if intermediate segment */ - else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&& - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)) - { - (DMA_RX_FRAME_infos->Seg_Count) ++; - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - return 0; -} - -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param DMATxDescTab: Pointer on the first Tx desc list - * @param TxBuff: Pointer on the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list - * @retval None - */ -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - DMATxDescToSet = DMATxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - DMATxDesc = DMATxDescTab + i; - /* Set Second Address Chained bit */ - DMATxDesc->Status = ETH_DMATxDesc_TCH; - - /* Set Buffer1 address pointer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Desciptor List Address Register */ - ETH->DMATDLAR = (uint32_t) DMATxDescTab; -} - -/** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param ETH_DMATxDescFlag: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine - * @arg ETH_DMATxDesc_IC : Interrupt on completion - * @arg ETH_DMATxDesc_LS : Last Segment - * @arg ETH_DMATxDesc_FS : First Segment - * @arg ETH_DMATxDesc_DC : Disable CRC - * @arg ETH_DMATxDesc_DP : Disable Pad - * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable - * @arg ETH_DMATxDesc_CIC : Checksum insertion control - * @arg ETH_DMATxDesc_TER : Transmit End of Ring - * @arg ETH_DMATxDesc_TCH : Second Address Chained - * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status - * @arg ETH_DMATxDesc_IHE : IP Header Error - * @arg ETH_DMATxDesc_ES : Error summary - * @arg ETH_DMATxDesc_JT : Jabber Timeout - * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush - * @arg ETH_DMATxDesc_PCE : Payload Checksum Error - * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during transmission - * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the transceiver - * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision - * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions - * @arg ETH_DMATxDesc_VF : VLAN Frame - * @arg ETH_DMATxDesc_CC : Collision Count - * @arg ETH_DMATxDesc_ED : Excessive Deferral - * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory - * @arg ETH_DMATxDesc_DB : Deferred Bit - * @retval The new state of ETH_DMATxDescFlag (SET or RESET). - */ -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); - - if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @retval The Transmit descriptor collision counter value. - */ -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) -{ - /* Return the Receive descriptor frame length */ - return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); -} - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param DMATxDesc: Pointer on a Tx desc - * @retval None - */ -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) -{ - /* Set the DMA Tx Desc Own bit */ - DMATxDesc->Status |= ETH_DMATxDesc_OWN; -} - -/** - * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. - * @param DMATxDesc: Pointer on a Tx desc - * @param NewState: new state of the DMA Tx Desc transmit interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA Tx Desc Transmit interrupt */ - DMATxDesc->Status |= ETH_DMATxDesc_IC; - } - else - { - /* Disable the DMA Tx Desc Transmit interrupt */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); - } -} - -/** - * @brief configure Tx descriptor as last or first segment - * @param DMATxDesc: Pointer on a Tx desc - * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. - * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment - * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment - * @retval None - */ -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); - - /* Selects the DMA Tx Desc Frame segment */ - DMATxDesc->Status |= DMATxDesc_FrameSegment; -} - -/** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass - * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum - * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); - - /* Set the selected DMA Tx desc checksum insertion control */ - DMATxDesc->Status |= DMATxDesc_Checksum; -} - -/** - * @brief Enables or disables the DMA Tx Desc CRC. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc CRC. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc CRC */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); - } - else - { - /* Disable the selected DMA Tx Desc CRC */ - DMATxDesc->Status |= ETH_DMATxDesc_DC; - } -} - -/** - * @brief Enables or disables the DMA Tx Desc second address chained. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc second address chained. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status |= ETH_DMATxDesc_TCH; - } - else - { - /* Disable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); - } -} - -/** - * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); - } - else - { - /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ - DMATxDesc->Status |= ETH_DMATxDesc_DP; - } -} - -/** - * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. - * @param DMATxDesc: Pointer on a Tx desc - * @param BufferSize1: specifies the Tx desc buffer1 size. - * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). - * @retval None - */ -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); - assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); - - /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ - DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); -} - -/** - * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param ETH_DMARxDescFlag: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine - * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame - * @arg ETH_DMARxDesc_ES: Error summary - * @arg ETH_DMARxDesc_DE: Descriptor error: no more descriptors for receive frame - * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame - * @arg ETH_DMARxDesc_LE: Frame size not matching with length field - * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow - * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame - * @arg ETH_DMARxDesc_FS: First descriptor of the frame - * @arg ETH_DMARxDesc_LS: Last descriptor of the frame - * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error - * @arg ETH_DMARxDesc_LC: Late collision occurred during reception - * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 - * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception - * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface - * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits - * @arg ETH_DMARxDesc_CE: CRC error - * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error - * @retval The new state of ETH_DMARxDescFlag (SET or RESET). - */ -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); - if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -#ifdef USE_ENHANCED_DMA_DESCRIPTORS -/** - * @brief Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not. - * @param DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor - * @param ETH_DMAPTPRxDescFlag: specifies the extended flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMAPTPRxDesc_PTPV: PTP version - * @arg ETH_DMAPTPRxDesc_PTPFT: PTP frame type - * @arg ETH_DMAPTPRxDesc_PTPMT: PTP message type - * @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received - * @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received - * @arg ETH_DMAPTPRxDesc_IPCB: IP checksum bypassed - * @arg ETH_DMAPTPRxDesc_IPPE: IP payload error - * @arg ETH_DMAPTPRxDesc_IPHE: IP header error - * @arg ETH_DMAPTPRxDesc_IPPT: IP payload type - * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET). - */ -FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(ETH_DMAPTPRxDescExtendedFlag)); - - if ((DMAPTPRxDesc->ExtendedStatus & ETH_DMAPTPRxDescExtendedFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param DMARxDesc: Pointer on a Rx desc - * @retval None - */ -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) -{ - /* Set the DMA Rx Desc Own bit */ - DMARxDesc->Status |= ETH_DMARxDesc_OWN; -} - -/** - * @brief Returns the specified DMA Rx Desc frame length. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @retval The Rx descriptor received frame length. - */ -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) -{ - /* Return the Receive descriptor frame length */ - return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); -} - -/** - * @brief Enables or disables the specified DMA Rx Desc receive interrupt. - * @param DMARxDesc: Pointer on a Rx desc - * @param NewState: new state of the specified DMA Rx Desc interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA Rx Desc receive interrupt */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); - } - else - { - /* Disable the DMA Rx Desc receive interrupt */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; - } -} - -/** - * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. - * This parameter can be any one of the following values: - * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 - * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 - * @retval The Receive descriptor frame length. - */ -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); - - if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) - { - /* Return the DMA Rx Desc buffer2 size */ - return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); - } - else - { - /* Return the DMA Rx Desc buffer1 size */ - return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); - } -} - -/** - * @brief Get the size of the received packet. - * @param None - * @retval framelength: received packet size - */ -uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc) -{ - uint32_t frameLength = 0; - if(((DMARxDesc->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDesc->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDesc->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET)) - { - /* Get the size of the packet: including 4 bytes of the CRC */ - frameLength = ETH_GetDMARxDescFrameLength(DMARxDesc); - } - - /* Return Frame Length */ - return frameLength; -} - -#ifdef USE_ENHANCED_DMA_DESCRIPTORS -/** - * @brief Enables or disables the Enhanced descriptor structure. - * @param NewState: new state of the Enhanced descriptor structure. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_EnhancedDescriptorCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable enhanced descriptor structure */ - ETH->DMABMR |= ETH_DMABMR_EDE; - } - else - { - /* Disable enhanced descriptor structure */ - ETH->DMABMR &= ~ETH_DMABMR_EDE; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->DMABMR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->DMABMR = tmpreg; -} -#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ - -/******************************************************************************/ -/* DMA functions */ -/******************************************************************************/ -/** - * @brief Resets all MAC subsystem internal registers and logic. - * @param None - * @retval None - */ -void ETH_SoftwareReset(void) -{ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - ETH->DMABMR |= ETH_DMABMR_SR; -} - -/** - * @brief Checks whether the ETHERNET software reset bit is set or not. - * @param None - * @retval The new state of DMA Bus Mode register SR bit (SET or RESET). - */ -FlagStatus ETH_GetSoftwareResetStatus(void) -{ - FlagStatus bitstatus = RESET; - if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param ETH_DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag - * @arg ETH_DMA_FLAG_PMT : PMT flag - * @arg ETH_DMA_FLAG_MMC : MMC flag - * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access - * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr - * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ET : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Underflow flag - * @arg ETH_DMA_FLAG_RO : Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); - if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the ETHERNET’s DMA pending flag. - * @param ETH_DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ETI : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag - * @arg ETH_DMA_FLAG_RO : Receive Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval None - */ -void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); - - /* Clear the selected ETHERNET DMA FLAG */ - ETH->DMASR = (uint32_t) ETH_DMA_FLAG; -} - -/** - * @brief Enables or disables the specified ETHERNET DMA interrupts. - * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @param NewState: new state of the specified ETHERNET DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET DMA interrupts */ - ETH->DMAIER |= ETH_DMA_IT; - } - else - { - /* Disable the selected ETHERNET DMA interrupts */ - ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); - } -} - -/** - * @brief Checks whether the specified ETHERNET DMA interrupt has occurred or not. - * @param ETH_DMA_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt - * @arg ETH_DMA_IT_PMT : PMT interrupt - * @arg ETH_DMA_IT_MMC : MMC interrupt - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @retval The new state of ETH_DMA_IT (SET or RESET). - */ -ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); - if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the ETHERNET’s DMA IT pending bit. - * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ETI : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt - * @arg ETH_DMA_IT_RO : Receive Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @retval None - */ -void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) -{ - /* Check the parameters */ - assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - - /* Clear the selected ETHERNET DMA IT */ - ETH->DMASR = (uint32_t) ETH_DMA_IT; -} - -/** - * @brief Returns the ETHERNET DMA Transmit Process State. - * @param None - * @retval The new ETHERNET DMA Transmit Process State: - * This can be one of the following values: - * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued - * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor - * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status - * - ETH_DMA_TransmitProcess_Reading : Running - reading the data from host memory - * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Descriptor unavailable - * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor - */ -uint32_t ETH_GetTransmitProcessState(void) -{ - return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); -} - -/** - * @brief Returns the ETHERNET DMA Receive Process State. - * @param None - * @retval The new ETHERNET DMA Receive Process State: - * This can be one of the following values: - * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued - * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor - * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet - * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Descriptor unavailable - * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor - * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the receive frame into host memory - */ -uint32_t ETH_GetReceiveProcessState(void) -{ - return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); -} - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param None - * @retval None - */ -void ETH_FlushTransmitFIFO(void) -{ - __IO uint32_t tmpreg = 0; - /* Set the Flush Transmit FIFO bit */ - ETH->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->DMAOMR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->DMAOMR = tmpreg; -} - -/** - * @brief Checks whether the ETHERNET flush transmit FIFO bit is cleared or not. - * @param None - * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET). - */ -FlagStatus ETH_GetFlushTransmitFIFOStatus(void) -{ - FlagStatus bitstatus = RESET; - if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Enables or disables the DMA transmission. - * @param NewState: new state of the DMA transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATransmissionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transmission */ - ETH->DMAOMR |= ETH_DMAOMR_ST; - } - else - { - /* Disable the DMA transmission */ - ETH->DMAOMR &= ~ETH_DMAOMR_ST; - } -} - -/** - * @brief Enables or disables the DMA reception. - * @param NewState: new state of the DMA reception. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMAReceptionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA reception */ - ETH->DMAOMR |= ETH_DMAOMR_SR; - } - else - { - /* Disable the DMA reception */ - ETH->DMAOMR &= ~ETH_DMAOMR_SR; - } -} - -/** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET). - */ -FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); - - if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. - * @param None - * @retval The value of Rx overflow Missed Frame Counter. - */ -uint32_t ETH_GetRxOverflowMissedFrameCounter(void) -{ - return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); -} - -/** - * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. - * @param None - * @retval The value of Buffer unavailable Missed Frame Counter. - */ -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) -{ - return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); -} - -/** - * @brief Get the ETHERNET DMA DMACHTDR register value. - * @param None - * @retval The value of the current Tx desc start address. - */ -uint32_t ETH_GetCurrentTxDescStartAddress(void) -{ - return ((uint32_t)(ETH->DMACHTDR)); -} - -/** - * @brief Get the ETHERNET DMA DMACHRDR register value. - * @param None - * @retval The value of the current Rx desc start address. - */ -uint32_t ETH_GetCurrentRxDescStartAddress(void) -{ - return ((uint32_t)(ETH->DMACHRDR)); -} - -/** - * @brief Get the ETHERNET DMA DMACHTBAR register value. - * @param None - * @retval The value of the current transmit descriptor data buffer address. - */ -uint32_t ETH_GetCurrentTxBufferAddress(void) -{ - return ((uint32_t)(ETH->DMACHTBAR)); -} - -/** - * @brief Get the ETHERNET DMA DMACHRBAR register value. - * @param None - * @retval The value of the current receive descriptor data buffer address. - */ -uint32_t ETH_GetCurrentRxBufferAddress(void) -{ - return ((uint32_t)(ETH->DMACHRBAR)); -} - -/** - * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register - * (the data written could be anything). This forces the DMA to resume transmission. - * @param None - * @retval None. - */ -void ETH_ResumeDMATransmission(void) -{ - ETH->DMATPDR = 0; -} - -/** - * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register - * (the data written could be anything). This forces the DMA to resume reception. - * @param None - * @retval None. - */ -void ETH_ResumeDMAReception(void) -{ - ETH->DMARPDR = 0; -} - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param Value: DMA Receive status watchdog timer register value - * @retval None - */ -void ETH_SetReceiveWatchdogTimer(uint8_t Value) -{ - /* Set the DMA Receive status watchdog timer register */ - ETH->DMARSWTR = Value; -} - -/******************************************************************************/ -/* PHY functions */ -/******************************************************************************/ - -/** - * @brief Read a PHY register - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. - * This parameter can be one of the following values: 0,..,31 - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * @arg PHY_BCR: Transceiver Basic Control Register - * @arg PHY_BSR: Transceiver Basic Status Register - * @arg PHY_SR : Transceiver Status Register - * @arg More PHY register could be read depending on the used PHY - * @retval ETH_ERROR: in case of timeout - * MAC MIIDR register value: Data read from the selected PHY register (correct read ) - */ -uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) -{ - uint32_t tmpreg = 0; - __IO uint32_t timeout = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_ETH_PHY_REG(PHYReg)); - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_MASK; - /* Prepare the MII address register value */ - tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA);/* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Write the result value into the MII Address register */ - ETH->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; - tmpreg = ETH->MACMIIAR; - } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - return (uint16_t)ETH_ERROR; - } - - /* Return data register value */ - return (uint16_t)(ETH->MACMIIDR); -} - -/** - * @brief Write to a PHY register - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. - * This parameter can be one of the following values: 0,..,31 - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * @arg PHY_BCR : Transceiver Control Register - * @arg More PHY register could be written depending on the used PHY - * @param PHYValue: the value to write - * @retval ETH_ERROR: in case of timeout - * ETH_SUCCESS: for correct write - */ -uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) -{ - uint32_t tmpreg = 0; - __IO uint32_t timeout = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_ETH_PHY_REG(PHYReg)); - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_MASK; - /* Prepare the MII register address value */ - tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Give the value to the MII data register */ - ETH->MACMIIDR = PHYValue; - /* Write the result value into the MII Address register */ - ETH->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; - tmpreg = ETH->MACMIIAR; - } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_WRITE_TO) - { - return ETH_ERROR; - } - - /* Return SUCCESS */ - return ETH_SUCCESS; -} - -/** - * @brief Enables or disables the PHY loopBack mode. - * @note: Don't be confused with ETH_MACLoopBackCmd function which enables internal - * loopback at MII level - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. - * @param NewState: new state of the PHY loopBack mode. - * This parameter can be: ENABLE or DISABLE. - * @retval ETH_ERROR: in case of bad PHY configuration - * ETH_SUCCESS: for correct PHY configuration - */ -uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the PHY configuration to update it */ - tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); - - if (NewState != DISABLE) - { - /* Enable the PHY loopback mode */ - tmpreg |= PHY_Loopback; - } - else - { - /* Disable the PHY loopback mode: normal mode */ - tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); - } - /* Update the PHY control register with the new configuration */ - if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) - { - return ETH_SUCCESS; - } - else - { - /* Return SUCCESS */ - return ETH_ERROR; - } -} - -/******************************************************************************/ -/* Power Management(PMT) functions */ -/******************************************************************************/ -/** - * @brief Reset Wakeup frame filter register pointer. - * @param None - * @retval None - */ -void ETH_ResetWakeUpFrameFilterRegisterPointer(void) -{ - __IO uint32_t tmpreg = 0; - /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACPMTCSR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACPMTCSR = tmpreg; -} - -/** - * @brief Populates the remote wakeup frame registers. - * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words). - * @retval None - */ -void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) -{ - __IO uint32_t tmpreg = 0; - uint32_t i = 0; - - /* Fill Remote Wake-up Frame Filter register with Buffer data */ - for(i =0; iMACRWUFFR = Buffer[i]; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACRWUFFR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACRWUFFR = tmpreg; - } -} - -/** - * @brief Enables or disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param NewState: new state of the MAC Global Unicast Wake-Up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC Global Unicast Wake-Up */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; - } - else - { - /* Disable the MAC Global Unicast Wake-Up */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACPMTCSR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACPMTCSR = tmpreg; -} - -/** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param ETH_PMT_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). - */ -FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); - - if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Enables or disables the MAC Wake-Up Frame Detection. - * @param NewState: new state of the MAC Wake-Up Frame Detection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC Wake-Up Frame Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; - } - else - { - /* Disable the MAC Wake-Up Frame Detection */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; - } - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACPMTCSR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACPMTCSR = tmpreg; -} - -/** - * @brief Enables or disables the MAC Magic Packet Detection. - * @param NewState: new state of the MAC Magic Packet Detection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MagicPacketDetectionCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC Magic Packet Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; - } - else - { - /* Disable the MAC Magic Packet Detection */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACPMTCSR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACPMTCSR = tmpreg; -} - -/** - * @brief Enables or disables the MAC Power Down. - * @param NewState: new state of the MAC Power Down. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_PowerDownCmd(FunctionalState NewState) -{ - __IO uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MAC Power Down */ - /* This puts the MAC in power down mode */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; - } - else - { - /* Disable the MAC Power Down */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = ETH->MACPMTCSR; - _eth_delay_(ETH_REG_WRITE_DELAY); - ETH->MACPMTCSR = tmpreg; -} - -/******************************************************************************/ -/* MMC functions */ -/******************************************************************************/ -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param None - * @retval None - */ -void ETH_MMCCounterFullPreset(void) -{ - /* Preset and Initialize the MMC counters to almost-full value */ - ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP; -} - -/** - * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16) - * @param None - * @retval None - */ -void ETH_MMCCounterHalfPreset(void) -{ - /* Preset the MMC counters to almost-full value */ - ETH->MMCCR &= ~ETH_MMCCR_MCFHP; - - /* Initialize the MMC counters to almost-half value */ - ETH->MMCCR |= ETH_MMCCR_MCP; -} - -/** - * @brief Enables or disables the MMC Counter Freeze. - * @param NewState: new state of the MMC Counter Freeze. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MMCCounterFreezeCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MMC Counter Freeze */ - ETH->MMCCR |= ETH_MMCCR_MCF; - } - else - { - /* Disable the MMC Counter Freeze */ - ETH->MMCCR &= ~ETH_MMCCR_MCF; - } -} - -/** - * @brief Enables or disables the MMC Reset On Read. - * @param NewState: new state of the MMC Reset On Read. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MMCResetOnReadCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the MMC Counter reset on read */ - ETH->MMCCR |= ETH_MMCCR_ROR; - } - else - { - /* Disable the MMC Counter reset on read */ - ETH->MMCCR &= ~ETH_MMCCR_ROR; - } -} - -/** - * @brief Enables or disables the MMC Counter Stop Rollover. - * @param NewState: new state of the MMC Counter Stop Rollover. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MMCCounterRolloverCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Disable the MMC Counter Stop Rollover */ - ETH->MMCCR &= ~ETH_MMCCR_CSR; - } - else - { - /* Enable the MMC Counter Stop Rollover */ - ETH->MMCCR |= ETH_MMCCR_CSR; - } -} - -/** - * @brief Resets the MMC Counters. - * @param None - * @retval None - */ -void ETH_MMCCountersReset(void) -{ - /* Resets the MMC Counters */ - ETH->MMCCR |= ETH_MMCCR_CR; -} - -/** - * @brief Enables or disables the specified ETHERNET MMC interrupts. - * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of Tx interrupt or - * any combination of Rx interrupt (but not both)of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @param NewState: new state of the specified ETHERNET MMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - /* Remove Register mak from IT */ - ETH_MMC_IT &= 0xEFFFFFFF; - - /* ETHERNET MMC Rx interrupts selected */ - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MMC interrupts */ - ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); - } - else - { - /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCRIMR |= ETH_MMC_IT; - } - } - else - { - /* ETHERNET MMC Tx interrupts selected */ - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MMC interrupts */ - ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); - } - else - { - /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCTIMR |= ETH_MMC_IT; - } - } -} - -/** - * @brief Checks whether the specified ETHERNET MMC IT is set or not. - * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value - * @retval The value of ETHERNET MMC IT (SET or RESET). - */ -ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); - - if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - /* ETHERNET MMC Rx interrupts selected */ - /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occurred */ - if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - /* ETHERNET MMC Tx interrupts selected */ - /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occurred */ - if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - - return bitstatus; -} - -/** - * @brief Get the specified ETHERNET MMC register value. - * @param ETH_MMCReg: specifies the ETHERNET MMC register. - * This parameter can be one of the following values: - * @arg ETH_MMCCR : MMC CR register - * @arg ETH_MMCRIR : MMC RIR register - * @arg ETH_MMCTIR : MMC TIR register - * @arg ETH_MMCRIMR : MMC RIMR register - * @arg ETH_MMCTIMR : MMC TIMR register - * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register - * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register - * @arg ETH_MMCTGFCR : MMC TGFCR register - * @arg ETH_MMCRFCECR : MMC RFCECR register - * @arg ETH_MMCRFAECR : MMC RFAECR register - * @arg ETH_MMCRGUFCR : MMC RGUFCRregister - * @retval The value of ETHERNET MMC Register value. - */ -uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) -{ - /* Check the parameters */ - assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); - - /* Return the selected register value */ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); -} - - - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.c b/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.c deleted file mode 100644 index 4441611..0000000 --- a/lib/src/STM32F4xx_StdPeriph_Driver/stm32f4xx_hal_eth.c +++ /dev/null @@ -1,2063 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_eth.c - * @author MCD Application Team - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Declare a ETH_HandleTypeDef handle structure, for example: - ETH_HandleTypeDef heth; - - (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - - (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - - (##) Initialize the related GPIO clocks - (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - - (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - (##) HAL_ETH_DMATxDescListInit(); for Transmission process - (##) HAL_ETH_DMARxDescListInit(); for Reception process - - (#)Enable MAC and DMA transmission and reception: - (##) HAL_ETH_Start(); - - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - the frame to MAC TX FIFO: - (##) HAL_ETH_TransmitFrame(); - - (#)Poll for a received frame in ETH RX DMA Descriptors and get received - frame parameters - (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) - - (#) Get a received frame when an ETH RX interrupt occurs: - (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) - - (#) Communicate with external PHY device: - (##) Read a specific register from the PHY - HAL_ETH_ReadPHYRegister(); - (##) Write data to a specific RHY register: - HAL_ETH_WritePHYRegister(); - - (#) Configure the Ethernet MAC after ETH peripheral initialization - HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - - (#) Configure the Ethernet DMA after ETH peripheral initialization - HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - - -@- The PTP protocol and the DMA descriptors ring mode are not supported - in this driver - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_eth.h" -#include "bsp.h" -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -// #ifdef HAL_ETH_MODULE_ENABLED - -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Constants ETH Private Constants - * @{ - */ -#define ETH_TIMEOUT_SWRESET 500U -#define ETH_TIMEOUT_LINKED_STATE 5000U -#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); -static void ETH_Delay(uint32_t mdelay); - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the Ethernet peripheral - (+) De-initialize the Ethernet peripheral - - @endverbatim - * @{ - */ - -/** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg1 = 0U, phyreg = 0U; - uint32_t hclk = 60000000U; - uint32_t tickstart = 0U; - uint32_t err = ETH_SUCCESS; - - /* Check the ETH peripheral state */ - if(heth == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); - assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); - assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - - if(heth->State == HAL_ETH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit(heth); - } - - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - RCC_APB2ENR_SYSCFGEN - - /* Select MII or RMII Mode*/ - SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); - SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - - /* Get tick */ - tickstart = getSysTick(); - - /* Wait for software reset */ - while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - /* Check for the Timeout */ - if((getSysTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { - heth->State= HAL_ETH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are - not available, please check your external PHY or the IO configuration */ - return HAL_TIMEOUT; - } - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg1 &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = SystemCoreClock; - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000U)&&(hclk < 35000000U)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000U)&&(hclk < 60000000U)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000U)&&(hclk < 100000000U)) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000U)&&(hclk < 150000000U)) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ - { - /* CSR Clock Range between 150-183 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; - - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY reset */ - delay(PHY_RESET_DELAY); - - if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) - { - /* Get tick */ - tickstart = getSysTick(); - - /* We wait for linked status */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((getSysTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - - - /* Enable Auto-Negotiation */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = getSysTick(); - - /* Wait until the auto-negotiation will be completed */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((getSysTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - - /* Read the result of the auto-negotiation */ - if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_100M; - } - } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | - (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY configuration */ - delay(PHY_CONFIG_DELAY); - } - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-Initializes the ETH peripheral. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) -{ - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspDeInit(heth); - - /* Set ETH HAL state to Disabled */ - heth->State= HAL_ETH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab Pointer to the first Tx desc list - * @param TxBuff Pointer to the first TxBuffer list - * @param TxBuffCount Number of the used Tx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *dmatxdesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0U; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - dmatxdesc = DMATxDescTab + i; - - /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - - /* Set Buffer1 address pointer */ - dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - /* Set the DMA Tx descriptors checksum insertion */ - dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab Pointer to the first Rx desc list - * @param RxBuff Pointer to the first RxBuffer list - * @param RxBuffCount Number of the used Rx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *DMARxDesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0U; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable Ethernet DMA Rx Descriptor interrupt */ - DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - /* Set Receive Descriptor List Address Register */ - (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * - @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a frame - HAL_ETH_TransmitFrame(); - (+) Receive a frame - HAL_ETH_GetReceivedFrame(); - HAL_ETH_GetReceivedFrame_IT(); - (+) Read from an External PHY register - HAL_ETH_ReadPHYRegister(); - (+) Write to an External PHY register - HAL_ETH_WritePHYRegister(); - - @endverbatim - - * @{ - */ - -/** - * @brief Sends an Ethernet frame. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param FrameLength Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) -{ - uint32_t bufcount = 0U, size = 0U, i = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0U) - { - /* Set ETH HAL state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - /* OWN bit set */ - heth->State = HAL_ETH_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Get the number of needed Tx buffers for the current frame */ - if (FrameLength > ETH_TX_BUF_SIZE) - { - bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) - { - bufcount++; - } - } - else - { - bufcount = 1U; - } - if (bufcount == 1U) - { - /* Set LAST and FIRST segment */ - heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; - /* Set frame size */ - heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* Point to next descriptor */ - heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - else - { - for (i=0U; i< bufcount; i++) - { - /* Clear FIRST and LAST segment bits */ - heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0U) - { - /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; - } - - /* Program size */ - heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - - if (i == (bufcount-1U)) - { - /* Setting the last segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; - heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); - } - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* point to next descriptor */ - heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - } - - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0U; - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Checks for received frames. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) -{ - uint32_t framelength = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Check the ETH state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Check if segment is not owned by DMA */ - /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) - { - /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) - { - /* increment segment count */ - (heth->RxFrameInfos).SegCount++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1U) - { - (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; - } - - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - heth->RxFrameInfos.length = framelength; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - /* point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - /* Check if first segment */ - else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) - { - (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; - (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - else - { - (heth->RxFrameInfos).SegCount++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief Gets the Received frame in interrupt mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) -{ - uint32_t descriptorscancounter = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set ETH HAL State to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Scan descriptors owned by CPU */ - while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) - { - /* Just for security */ - descriptorscancounter++; - - /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ - if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ - else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) - { - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); - } - /* Should be last segment */ - else - { - /* Last segment */ - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1U) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - } - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - } - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief This function handles ETH interrupt request. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) -{ - /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) - { - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - } - /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) - { - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - - /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) - { - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback(heth); - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Ethernet transfer error callbacks - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Reads a PHY register - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue PHY register value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) -{ - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_RD) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - /* Get tick */ - tickstart = getSysTick(); - - /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((getSysTick() - tickstart ) > PHY_READ_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg1 = heth->Instance->MACMIIAR; - } - - /* Get MACMIIDR value */ - *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Writes to a PHY register. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue the value to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) -{ - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_WR) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = (uint16_t)RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - /* Get tick */ - tickstart = getSysTick(); - - /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((getSysTick() - tickstart ) > PHY_WRITE_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg1 = heth->Instance->MACMIIAR; - } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable MAC and DMA transmission and reception. - HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. - HAL_ETH_Stop(); - (+) Set the MAC configuration in runtime mode - HAL_ETH_ConfigMAC(); - (+) Set the DMA configuration in runtime mode - HAL_ETH_ConfigDMA(); - -@endverbatim - * @{ - */ - - /** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable(heth); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Start DMA transmission */ - ETH_DMATransmissionEnable(heth); - - /* Start DMA reception */ - ETH_DMAReceptionEnable(heth); - - /* Set the ETH state to READY*/ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Stop DMA transmission */ - ETH_DMATransmissionDisable(heth); - - /* Stop DMA reception */ - ETH_DMAReceptionDisable(heth); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable(heth); - - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set ETH MAC Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf MAC Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) -{ - uint32_t tmpreg1 = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - if (macconf != NULL) - { - /* Check the parameters */ - assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); - assert_param(IS_ETH_JABBER(macconf->Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); - assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - (heth->Init).Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | - macconf->VLANTagIdentifier); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ - { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - - /* Clear FES and DM bits */ - tmpreg1 &= ~(0x00004800U); - - tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - } - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets ETH DMA Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf DMA Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) -{ - uint32_t tmpreg1 = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); - assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * - @verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - (+) Get the ETH handle state: - HAL_ETH_GetState(); - - - @endverbatim - * @{ - */ - -/** - * @brief Return the ETH HAL state - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ - /* Return ETH state */ - return heth->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions - * @{ - */ - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param err Ethernet Init error - * @retval HAL status - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) -{ - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg1 = 0U; - - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - - /* Set Ethernet speed to 100M */ - (heth->Init).Speed = ETH_SPEED_100M; - } - - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0U; - macinit.HashTableLow = 0x0U; - macinit.PauseTime = 0x0U; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0U; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg1 &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg1 |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - (heth->Init).Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | - macinit.VLANTagIdentifier); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0U; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - (dmainit.DescriptorSkipLength << 2U) | - dmainit.DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); -} - -/** - * @brief Configures the selected MAC address. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param MacAddr The MAC address to configure - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 - * @arg ETH_MAC_Address2: MAC Address2 - * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg1; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - - /* Calculate the selected MAC address high register */ - tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; - /* Load the selected MAC address high register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; - /* Calculate the selected MAC address low register */ - tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; - - /* Load the selected MAC address low register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; -} - -/** - * @brief Enables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Enable the MAC transmission */ - (heth->Instance)->MACCR |= ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} - -/** - * @brief Disables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Disable the MAC transmission */ - (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} - -/** - * @brief Enables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Enable the MAC reception */ - (heth->Instance)->MACCR |= ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} - -/** - * @brief Disables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} - -/** - * @brief Enables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; -} - -/** - * @brief Disables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA transmission */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; -} - -/** - * @brief Enables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; -} - -/** - * @brief Disables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA reception */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; -} - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; -} - -/** - * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay specifies the delay time length, in milliseconds. - * @retval None - */ -static void ETH_Delay(uint32_t mdelay) -{ - __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do - { - __NOP(); - } - while (Delay --); -} - -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -// #endif /* HAL_ETH_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/